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-rw-r--r--src/mem/protocol/MESI_Two_Level-dma.sm84
-rw-r--r--src/mem/protocol/MI_example-dma.sm84
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-dma.sm4
-rw-r--r--src/mem/protocol/MOESI_CMP_token-dma.sm82
-rw-r--r--src/mem/protocol/MOESI_hammer-dma.sm84
-rw-r--r--src/mem/protocol/RubySlicc_Types.sm4
6 files changed, 283 insertions, 59 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm
index 68cb7e968..ecda3bd03 100644
--- a/src/mem/protocol/MESI_Two_Level-dma.sm
+++ b/src/mem/protocol/MESI_Two_Level-dma.sm
@@ -50,15 +50,38 @@ machine(MachineType:DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
- State cur_state;
+ structure(TBE, desc="...") {
+ State TBEState, desc="Transient state";
+ DataBlock DataBlk, desc="Data";
+ }
+
+ structure(TBETable, external = "yes") {
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
+ }
+
+ void set_tbe(TBE b);
+ void unset_tbe();
+ void wakeUpAllBuffers();
+
+ TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
+
Tick clockEdge();
- State getState(Addr addr) {
- return cur_state;
+ State getState(TBE tbe, Addr addr) {
+ if (is_valid(tbe)) {
+ return tbe.TBEState;
+ } else {
+ return State:READY;
+ }
}
- void setState(Addr addr, State state) {
- cur_state := state;
+ void setState(TBE tbe, Addr addr, State state) {
+ if (is_valid(tbe)) {
+ tbe.TBEState := state;
+ }
}
AccessPermission getAccessPermission(Addr addr) {
@@ -82,9 +105,9 @@ machine(MachineType:DMA, "DMA Controller")
if (dmaRequestQueue_in.isReady(clockEdge())) {
peek(dmaRequestQueue_in, SequencerMsg) {
if (in_msg.Type == SequencerRequestType:LD ) {
- trigger(Event:ReadRequest, in_msg.LineAddress);
+ trigger(Event:ReadRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
} else if (in_msg.Type == SequencerRequestType:ST) {
- trigger(Event:WriteRequest, in_msg.LineAddress);
+ trigger(Event:WriteRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
} else {
error("Invalid request type");
}
@@ -96,9 +119,11 @@ machine(MachineType:DMA, "DMA Controller")
if (dmaResponseQueue_in.isReady(clockEdge())) {
peek( dmaResponseQueue_in, ResponseMsg) {
if (in_msg.Type == CoherenceResponseType:ACK) {
- trigger(Event:Ack, makeLineAddress(in_msg.addr));
+ trigger(Event:Ack, makeLineAddress(in_msg.addr),
+ TBEs[makeLineAddress(in_msg.addr)]);
} else if (in_msg.Type == CoherenceResponseType:DATA) {
- trigger(Event:Data, makeLineAddress(in_msg.addr));
+ trigger(Event:Data, makeLineAddress(in_msg.addr),
+ TBEs[makeLineAddress(in_msg.addr)]);
} else {
error("Invalid response type");
}
@@ -133,15 +158,30 @@ machine(MachineType:DMA, "DMA Controller")
}
action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
- dma_sequencer.ackCallback();
+ dma_sequencer.ackCallback(address);
}
action(d_dataCallback, "d", desc="Write data to dma sequencer") {
- peek (dmaResponseQueue_in, ResponseMsg) {
- dma_sequencer.dataCallback(in_msg.DataBlk);
+ dma_sequencer.dataCallback(tbe.DataBlk, address);
+ }
+
+ action(t_updateTBEData, "t", desc="Update TBE Data") {
+ assert(is_valid(tbe));
+ peek( dmaResponseQueue_in, ResponseMsg) {
+ tbe.DataBlk := in_msg.DataBlk;
}
}
+ action(v_allocateTBE, "v", desc="Allocate TBE entry") {
+ TBEs.allocate(address);
+ set_tbe(TBEs[address]);
+ }
+
+ action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
+ TBEs.deallocate(address);
+ unset_tbe();
+ }
+
action(p_popRequestQueue, "p", desc="Pop request queue") {
dmaRequestQueue_in.dequeue(clockEdge());
}
@@ -150,23 +190,43 @@ machine(MachineType:DMA, "DMA Controller")
dmaResponseQueue_in.dequeue(clockEdge());
}
+ action(zz_stallAndWaitRequestQueue, "zz", desc="...") {
+ stall_and_wait(dmaRequestQueue_in, address);
+ }
+
+ action(wkad_wakeUpAllDependents, "wkad", desc="wake-up all dependents") {
+ wakeUpAllBuffers();
+ }
+
transition(READY, ReadRequest, BUSY_RD) {
+ v_allocateTBE;
s_sendReadRequest;
p_popRequestQueue;
}
transition(READY, WriteRequest, BUSY_WR) {
+ v_allocateTBE;
s_sendWriteRequest;
p_popRequestQueue;
}
transition(BUSY_RD, Data, READY) {
+ t_updateTBEData;
d_dataCallback;
+ w_deallocateTBE;
p_popResponseQueue;
+ wkad_wakeUpAllDependents;
}
transition(BUSY_WR, Ack, READY) {
a_ackCallback;
+ w_deallocateTBE;
p_popResponseQueue;
+ wkad_wakeUpAllDependents;
}
+
+ transition({BUSY_RD,BUSY_WR}, {ReadRequest,WriteRequest}) {
+ zz_stallAndWaitRequestQueue;
+ }
+
}
diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm
index 6032229ee..aebdce81c 100644
--- a/src/mem/protocol/MI_example-dma.sm
+++ b/src/mem/protocol/MI_example-dma.sm
@@ -50,17 +50,38 @@ machine(MachineType:DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
- State cur_state;
+ structure(TBE, desc="...") {
+ State TBEState, desc="Transient state";
+ DataBlock DataBlk, desc="Data";
+ }
+
+ structure(TBETable, external = "yes") {
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
+ }
+
+ void set_tbe(TBE b);
+ void unset_tbe();
+ void wakeUpAllBuffers();
+
+ TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
Tick clockEdge();
- Cycles ticksToCycles(Tick t);
- State getState(Addr addr) {
- return cur_state;
+ State getState(TBE tbe, Addr addr) {
+ if (is_valid(tbe)) {
+ return tbe.TBEState;
+ } else {
+ return State:READY;
+ }
}
- void setState(Addr addr, State state) {
- cur_state := state;
+ void setState(TBE tbe, Addr addr, State state) {
+ if (is_valid(tbe)) {
+ tbe.TBEState := state;
+ }
}
AccessPermission getAccessPermission(Addr addr) {
@@ -84,9 +105,9 @@ machine(MachineType:DMA, "DMA Controller")
if (dmaRequestQueue_in.isReady(clockEdge())) {
peek(dmaRequestQueue_in, SequencerMsg) {
if (in_msg.Type == SequencerRequestType:LD ) {
- trigger(Event:ReadRequest, in_msg.LineAddress);
+ trigger(Event:ReadRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
} else if (in_msg.Type == SequencerRequestType:ST) {
- trigger(Event:WriteRequest, in_msg.LineAddress);
+ trigger(Event:WriteRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
} else {
error("Invalid request type");
}
@@ -98,9 +119,9 @@ machine(MachineType:DMA, "DMA Controller")
if (dmaResponseQueue_in.isReady(clockEdge())) {
peek( dmaResponseQueue_in, DMAResponseMsg) {
if (in_msg.Type == DMAResponseType:ACK) {
- trigger(Event:Ack, in_msg.LineAddress);
+ trigger(Event:Ack, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
} else if (in_msg.Type == DMAResponseType:DATA) {
- trigger(Event:Data, in_msg.LineAddress);
+ trigger(Event:Data, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
} else {
error("Invalid response type");
}
@@ -139,17 +160,30 @@ machine(MachineType:DMA, "DMA Controller")
}
action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
- peek (dmaResponseQueue_in, DMAResponseMsg) {
- dma_sequencer.ackCallback();
- }
+ dma_sequencer.ackCallback(address);
}
action(d_dataCallback, "d", desc="Write data to dma sequencer") {
- peek (dmaResponseQueue_in, DMAResponseMsg) {
- dma_sequencer.dataCallback(in_msg.DataBlk);
+ dma_sequencer.dataCallback(tbe.DataBlk, address);
+ }
+
+ action(t_updateTBEData, "t", desc="Update TBE Data") {
+ assert(is_valid(tbe));
+ peek( dmaResponseQueue_in, DMAResponseMsg) {
+ tbe.DataBlk := in_msg.DataBlk;
}
}
+ action(v_allocateTBE, "v", desc="Allocate TBE entry") {
+ TBEs.allocate(address);
+ set_tbe(TBEs[address]);
+ }
+
+ action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
+ TBEs.deallocate(address);
+ unset_tbe();
+ }
+
action(p_popRequestQueue, "p", desc="Pop request queue") {
dmaRequestQueue_in.dequeue(clockEdge());
}
@@ -158,23 +192,43 @@ machine(MachineType:DMA, "DMA Controller")
dmaResponseQueue_in.dequeue(clockEdge());
}
+ action(zz_stallAndWaitRequestQueue, "zz", desc="...") {
+ stall_and_wait(dmaRequestQueue_in, address);
+ }
+
+ action(wkad_wakeUpAllDependents, "wkad", desc="wake-up all dependents") {
+ wakeUpAllBuffers();
+ }
+
transition(READY, ReadRequest, BUSY_RD) {
+ v_allocateTBE;
s_sendReadRequest;
p_popRequestQueue;
}
transition(READY, WriteRequest, BUSY_WR) {
+ v_allocateTBE;
s_sendWriteRequest;
p_popRequestQueue;
}
transition(BUSY_RD, Data, READY) {
+ t_updateTBEData;
d_dataCallback;
+ w_deallocateTBE;
p_popResponseQueue;
+ wkad_wakeUpAllDependents;
}
transition(BUSY_WR, Ack, READY) {
a_ackCallback;
+ w_deallocateTBE;
p_popResponseQueue;
+ wkad_wakeUpAllDependents;
}
+
+ transition({BUSY_RD,BUSY_WR}, {ReadRequest,WriteRequest}) {
+ zz_stallAndWaitRequestQueue;
+ }
+
}
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm
index 5eb2f2587..ccc7f8790 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -184,7 +184,7 @@ machine(MachineType:DMA, "DMA Controller")
}
action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
- dma_sequencer.ackCallback();
+ dma_sequencer.ackCallback(address);
}
action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
@@ -236,7 +236,7 @@ machine(MachineType:DMA, "DMA Controller")
action(d_dataCallbackFromTBE, "/d", desc="data callback with data from TBE") {
assert(is_valid(tbe));
- dma_sequencer.dataCallback(tbe.DataBlk);
+ dma_sequencer.dataCallback(tbe.DataBlk, address);
}
action(v_allocateTBE, "v", desc="Allocate TBE entry") {
diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm
index 3b144771d..01152100b 100644
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dma.sm
@@ -52,16 +52,38 @@ machine(MachineType:DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
- State cur_state;
+ structure(TBE, desc="...") {
+ State TBEState, desc="Transient state";
+ DataBlock DataBlk, desc="Data";
+ }
+
+ structure(TBETable, external = "yes") {
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
+ }
+
+ void set_tbe(TBE b);
+ void unset_tbe();
+ void wakeUpAllBuffers();
+
+ TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
Tick clockEdge();
- State getState(Addr addr) {
- return cur_state;
+ State getState(TBE tbe, Addr addr) {
+ if (is_valid(tbe)) {
+ return tbe.TBEState;
+ } else {
+ return State:READY;
+ }
}
- void setState(Addr addr, State state) {
- cur_state := state;
+ void setState(TBE tbe, Addr addr, State state) {
+ if (is_valid(tbe)) {
+ tbe.TBEState := state;
+ }
}
AccessPermission getAccessPermission(Addr addr) {
@@ -85,9 +107,9 @@ machine(MachineType:DMA, "DMA Controller")
if (dmaRequestQueue_in.isReady(clockEdge())) {
peek(dmaRequestQueue_in, SequencerMsg) {
if (in_msg.Type == SequencerRequestType:LD ) {
- trigger(Event:ReadRequest, in_msg.LineAddress);
+ trigger(Event:ReadRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
} else if (in_msg.Type == SequencerRequestType:ST) {
- trigger(Event:WriteRequest, in_msg.LineAddress);
+ trigger(Event:WriteRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
} else {
error("Invalid request type");
}
@@ -99,9 +121,9 @@ machine(MachineType:DMA, "DMA Controller")
if (dmaResponseQueue_in.isReady(clockEdge())) {
peek( dmaResponseQueue_in, DMAResponseMsg) {
if (in_msg.Type == DMAResponseType:ACK) {
- trigger(Event:Ack, in_msg.LineAddress);
+ trigger(Event:Ack, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
} else if (in_msg.Type == DMAResponseType:DATA) {
- trigger(Event:Data, in_msg.LineAddress);
+ trigger(Event:Data, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
} else {
error("Invalid response type");
}
@@ -140,17 +162,30 @@ machine(MachineType:DMA, "DMA Controller")
}
action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
- peek (dmaResponseQueue_in, DMAResponseMsg) {
- dma_sequencer.ackCallback();
- }
+ dma_sequencer.ackCallback(address);
}
action(d_dataCallback, "d", desc="Write data to dma sequencer") {
- peek (dmaResponseQueue_in, DMAResponseMsg) {
- dma_sequencer.dataCallback(in_msg.DataBlk);
+ dma_sequencer.dataCallback(tbe.DataBlk, address);
+ }
+
+ action(t_updateTBEData, "t", desc="Update TBE Data") {
+ assert(is_valid(tbe));
+ peek(dmaResponseQueue_in, DMAResponseMsg) {
+ tbe.DataBlk := in_msg.DataBlk;
}
}
+ action(v_allocateTBE, "v", desc="Allocate TBE entry") {
+ TBEs.allocate(address);
+ set_tbe(TBEs[address]);
+ }
+
+ action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
+ TBEs.deallocate(address);
+ unset_tbe();
+ }
+
action(p_popRequestQueue, "p", desc="Pop request queue") {
dmaRequestQueue_in.dequeue(clockEdge());
}
@@ -159,23 +194,42 @@ machine(MachineType:DMA, "DMA Controller")
dmaResponseQueue_in.dequeue(clockEdge());
}
+ action(zz_stallAndWaitRequestQueue, "zz", desc="...") {
+ stall_and_wait(dmaRequestQueue_in, address);
+ }
+
+ action(wkad_wakeUpAllDependents, "wkad", desc="wake-up all dependents") {
+ wakeUpAllBuffers();
+ }
+
transition(READY, ReadRequest, BUSY_RD) {
+ v_allocateTBE;
s_sendReadRequest;
p_popRequestQueue;
}
transition(READY, WriteRequest, BUSY_WR) {
+ v_allocateTBE;
s_sendWriteRequest;
p_popRequestQueue;
}
transition(BUSY_RD, Data, READY) {
+ t_updateTBEData;
d_dataCallback;
+ w_deallocateTBE;
p_popResponseQueue;
+ wkad_wakeUpAllDependents;
}
transition(BUSY_WR, Ack, READY) {
a_ackCallback;
+ w_deallocateTBE;
p_popResponseQueue;
+ wkad_wakeUpAllDependents;
+ }
+
+ transition({BUSY_RD,BUSY_WR}, {ReadRequest,WriteRequest}) {
+ zz_stallAndWaitRequestQueue;
}
}
diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/protocol/MOESI_hammer-dma.sm
index 3592e9991..0e4b4f663 100644
--- a/src/mem/protocol/MOESI_hammer-dma.sm
+++ b/src/mem/protocol/MOESI_hammer-dma.sm
@@ -50,15 +50,38 @@ machine(MachineType:DMA, "DMA Controller")
Ack, desc="DMA write to memory completed";
}
- State cur_state;
+ structure(TBE, desc="...") {
+ State TBEState, desc="Transient state";
+ DataBlock DataBlk, desc="Data";
+ }
+
+ structure(TBETable, external = "yes") {
+ TBE lookup(Addr);
+ void allocate(Addr);
+ void deallocate(Addr);
+ bool isPresent(Addr);
+ }
+
+ void set_tbe(TBE b);
+ void unset_tbe();
+ void wakeUpAllBuffers();
+
+ TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
Tick clockEdge();
- State getState(Addr addr) {
- return cur_state;
+ State getState(TBE tbe, Addr addr) {
+ if (is_valid(tbe)) {
+ return tbe.TBEState;
+ } else {
+ return State:READY;
+ }
}
- void setState(Addr addr, State state) {
- cur_state := state;
+
+ void setState(TBE tbe, Addr addr, State state) {
+ if (is_valid(tbe)) {
+ tbe.TBEState := state;
+ }
}
AccessPermission getAccessPermission(Addr addr) {
@@ -82,9 +105,9 @@ machine(MachineType:DMA, "DMA Controller")
if (dmaRequestQueue_in.isReady(clockEdge())) {
peek(dmaRequestQueue_in, SequencerMsg) {
if (in_msg.Type == SequencerRequestType:LD ) {
- trigger(Event:ReadRequest, in_msg.LineAddress);
+ trigger(Event:ReadRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
} else if (in_msg.Type == SequencerRequestType:ST) {
- trigger(Event:WriteRequest, in_msg.LineAddress);
+ trigger(Event:WriteRequest, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
} else {
error("Invalid request type");
}
@@ -96,9 +119,9 @@ machine(MachineType:DMA, "DMA Controller")
if (dmaResponseQueue_in.isReady(clockEdge())) {
peek( dmaResponseQueue_in, DMAResponseMsg) {
if (in_msg.Type == DMAResponseType:ACK) {
- trigger(Event:Ack, in_msg.LineAddress);
+ trigger(Event:Ack, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
} else if (in_msg.Type == DMAResponseType:DATA) {
- trigger(Event:Data, in_msg.LineAddress);
+ trigger(Event:Data, in_msg.LineAddress, TBEs[in_msg.LineAddress]);
} else {
error("Invalid response type");
}
@@ -137,17 +160,30 @@ machine(MachineType:DMA, "DMA Controller")
}
action(a_ackCallback, "a", desc="Notify dma controller that write request completed") {
- peek (dmaResponseQueue_in, DMAResponseMsg) {
- dma_sequencer.ackCallback();
- }
+ dma_sequencer.ackCallback(address);
}
action(d_dataCallback, "d", desc="Write data to dma sequencer") {
- peek (dmaResponseQueue_in, DMAResponseMsg) {
- dma_sequencer.dataCallback(in_msg.DataBlk);
+ dma_sequencer.dataCallback(tbe.DataBlk, address);
+ }
+
+ action(t_updateTBEData, "t", desc="Update TBE Data") {
+ assert(is_valid(tbe));
+ peek( dmaResponseQueue_in, DMAResponseMsg) {
+ tbe.DataBlk := in_msg.DataBlk;
}
}
+ action(v_allocateTBE, "v", desc="Allocate TBE entry") {
+ TBEs.allocate(address);
+ set_tbe(TBEs[address]);
+ }
+
+ action(w_deallocateTBE, "w", desc="Deallocate TBE entry") {
+ TBEs.deallocate(address);
+ unset_tbe();
+ }
+
action(p_popRequestQueue, "p", desc="Pop request queue") {
dmaRequestQueue_in.dequeue(clockEdge());
}
@@ -156,23 +192,43 @@ machine(MachineType:DMA, "DMA Controller")
dmaResponseQueue_in.dequeue(clockEdge());
}
+ action(zz_stallAndWaitRequestQueue, "zz", desc="...") {
+ stall_and_wait(dmaRequestQueue_in, address);
+ }
+
+ action(wkad_wakeUpAllDependents, "wkad", desc="wake-up all dependents") {
+ wakeUpAllBuffers();
+ }
+
transition(READY, ReadRequest, BUSY_RD) {
+ v_allocateTBE;
s_sendReadRequest;
p_popRequestQueue;
}
transition(READY, WriteRequest, BUSY_WR) {
+ v_allocateTBE;
s_sendWriteRequest;
p_popRequestQueue;
}
transition(BUSY_RD, Data, READY) {
+ t_updateTBEData;
d_dataCallback;
+ w_deallocateTBE;
p_popResponseQueue;
+ wkad_wakeUpAllDependents;
}
transition(BUSY_WR, Ack, READY) {
a_ackCallback;
+ w_deallocateTBE;
p_popResponseQueue;
+ wkad_wakeUpAllDependents;
}
+
+ transition({BUSY_RD,BUSY_WR}, {ReadRequest,WriteRequest}) {
+ zz_stallAndWaitRequestQueue;
+ }
+
}
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index e8a739eb4..27a045d29 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -220,8 +220,8 @@ structure (WireBuffer, inport="yes", outport="yes", external = "yes") {
}
structure (DMASequencer, external = "yes") {
- void ackCallback();
- void dataCallback(DataBlock);
+ void ackCallback(Addr);
+ void dataCallback(DataBlock,Addr);
void recordRequestType(CacheRequestType);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-03 00:28:18 +0000