diff options
Diffstat (limited to 'src/mem/protocol')
22 files changed, 336 insertions, 266 deletions
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm index f707ba963..49b6aa7a9 100644 --- a/src/mem/protocol/MESI_Three_Level-L0cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm @@ -33,14 +33,13 @@ machine(L0Cache, "MESI Directory L0 Cache") Cycles request_latency := 2; Cycles response_latency := 2; bool send_evictions; -{ - // NODE L0 CACHE - // From this node's L0 cache to the network - MessageBuffer bufferToL1, network="To", physical_network="0", ordered="true"; - // To this node's L0 cache FROM the network - MessageBuffer bufferFromL1, network="From", physical_network="0", ordered="true"; + // From this node's L0 cache to the network + MessageBuffer * bufferToL1, network="To", ordered="true"; + // To this node's L0 cache FROM the network + MessageBuffer * bufferFromL1, network="From", ordered="true"; +{ // Message queue between this controller and the processor MessageBuffer mandatoryQueue, ordered="false"; diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm index 170599a51..59249d822 100644 --- a/src/mem/protocol/MESI_Three_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm @@ -32,26 +32,30 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") Cycles l1_request_latency := 2; Cycles l1_response_latency := 2; Cycles to_l2_latency := 1; -{ - // From this node's L1 cache TO the network - // a local L1 -> this L2 bank, currently ordered with directory forwarded requests - MessageBuffer requestToL2, network="To", virtual_network="0", ordered="false", vnet_type="request"; - // a local L1 -> this L2 bank - MessageBuffer responseToL2, network="To", virtual_network="1", ordered="false", vnet_type="response"; - MessageBuffer unblockToL2, network="To", virtual_network="2", ordered="false", vnet_type="unblock"; - - // To this node's L1 cache FROM the network - // a L2 bank -> this L1 - MessageBuffer requestFromL2, network="From", virtual_network="0", ordered="false", vnet_type="request"; - // a L2 bank -> this L1 - MessageBuffer responseFromL2, network="From", virtual_network="1", ordered="false", vnet_type="response"; - - // Message Buffers between the L1 and the L0 Cache - // From the L1 cache to the L0 cache - MessageBuffer bufferToL0, network="To", physical_network="0", ordered="true"; - // From the L0 cache to the L1 cache - MessageBuffer bufferFromL0, network="From", physical_network="0", ordered="true"; + // Message Buffers between the L1 and the L0 Cache + // From the L1 cache to the L0 cache + MessageBuffer * bufferToL0, network="To", ordered="true"; + + // From the L0 cache to the L1 cache + MessageBuffer * bufferFromL0, network="From", ordered="true"; + + // Message queue from this L1 cache TO the network / L2 + MessageBuffer * requestToL2, network="To", virtual_network="0", + ordered="false", vnet_type="request"; + + MessageBuffer * responseToL2, network="To", virtual_network="1", + ordered="false", vnet_type="response"; + MessageBuffer * unblockToL2, network="To", virtual_network="2", + ordered="false", vnet_type="unblock"; + + // To this L1 cache FROM the network / L2 + MessageBuffer * requestFromL2, network="From", virtual_network="2", + ordered="false", vnet_type="request"; + MessageBuffer * responseFromL2, network="From", virtual_network="1", + ordered="false", vnet_type="response"; + +{ // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { // Base states diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm index 96c1699b7..6c98c23e9 100644 --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm @@ -37,25 +37,34 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") Cycles to_l2_latency := 1; bool send_evictions; bool enable_prefetch := "False"; + + // Message Queues + // From this node's L1 cache TO the network + + // a local L1 -> this L2 bank, currently ordered with directory forwarded requests + MessageBuffer * requestFromL1Cache, network="To", virtual_network="0", + ordered="false", vnet_type="request"; + + // a local L1 -> this L2 bank + MessageBuffer * responseFromL1Cache, network="To", virtual_network="1", + ordered="false", vnet_type="response"; + + MessageBuffer * unblockFromL1Cache, network="To", virtual_network="2", + ordered="false", vnet_type="unblock"; + + + // To this node's L1 cache FROM the network + // a L2 bank -> this L1 + MessageBuffer * requestToL1Cache, network="From", virtual_network="2", + ordered="false", vnet_type="request"; + + // a L2 bank -> this L1 + MessageBuffer * responseToL1Cache, network="From", virtual_network="1", + ordered="false", vnet_type="response"; { - // NODE L1 CACHE - // From this node's L1 cache TO the network - // a local L1 -> this L2 bank, currently ordered with directory forwarded requests - MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false", vnet_type="request"; - // a local L1 -> this L2 bank - MessageBuffer responseFromL1Cache, network="To", virtual_network="1", ordered="false", vnet_type="response"; - MessageBuffer unblockFromL1Cache, network="To", virtual_network="2", ordered="false", vnet_type="unblock"; - - - // To this node's L1 cache FROM the network - // a L2 bank -> this L1 - MessageBuffer requestToL1Cache, network="From", virtual_network="0", ordered="false", vnet_type="request"; - // a L2 bank -> this L1 - MessageBuffer responseToL1Cache, network="From", virtual_network="1", ordered="false", vnet_type="response"; // Request Buffer for prefetches MessageBuffer optionalQueue, ordered="false"; - // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { // Base states diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm index f191ddccb..9e0522ea2 100644 --- a/src/mem/protocol/MESI_Two_Level-L2cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm @@ -26,34 +26,33 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* - * $Id: MSI_MOSI_CMP_directory-L2cache.sm 1.12 05/01/19 15:55:40-06:00 beckmann@s0-28.cs.wisc.edu $ - * - */ - machine(L2Cache, "MESI Directory L2 Cache CMP") : CacheMemory * L2cache; Cycles l2_request_latency := 2; Cycles l2_response_latency := 2; Cycles to_l1_latency := 1; -{ - // L2 BANK QUEUES + + // Message Queues // From local bank of L2 cache TO the network - MessageBuffer DirRequestFromL2Cache, network="To", virtual_network="0", + MessageBuffer * DirRequestFromL2Cache, network="To", virtual_network="0", ordered="false", vnet_type="request"; // this L2 bank -> Memory - MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="0", + + MessageBuffer * L1RequestFromL2Cache, network="To", virtual_network="2", ordered="false", vnet_type="request"; // this L2 bank -> a local L1 - MessageBuffer responseFromL2Cache, network="To", virtual_network="1", + + MessageBuffer * responseFromL2Cache, network="To", virtual_network="1", ordered="false", vnet_type="response"; // this L2 bank -> a local L1 || Memory // FROM the network to this local bank of L2 cache - MessageBuffer unblockToL2Cache, network="From", virtual_network="2", + MessageBuffer * unblockToL2Cache, network="From", virtual_network="2", ordered="false", vnet_type="unblock"; // a local L1 || Memory -> this L2 bank - MessageBuffer L1RequestToL2Cache, network="From", virtual_network="0", + + MessageBuffer * L1RequestToL2Cache, network="From", virtual_network="0", ordered="false", vnet_type="request"; // a local L1 -> this L2 bank - MessageBuffer responseToL2Cache, network="From", virtual_network="1", - ordered="false", vnet_type="response"; // a local L1 || Memory -> this L2 bank + MessageBuffer * responseToL2Cache, network="From", virtual_network="1", + ordered="false", vnet_type="response"; // a local L1 || Memory -> this L2 bank +{ // STATES state_declaration(State, desc="L2 Cache states", default="L2Cache_State_NP") { // Base states diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/protocol/MESI_Two_Level-dir.sm index 679f2dee7..dd0ecf49e 100644 --- a/src/mem/protocol/MESI_Two_Level-dir.sm +++ b/src/mem/protocol/MESI_Two_Level-dir.sm @@ -26,27 +26,19 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* - * $Id: MOESI_CMP_token-dir.sm 1.6 05/01/19 15:48:35-06:00 mikem@royal16.cs.wisc.edu $ - */ - -// This file is copied from Yasuko Watanabe's prefetch / memory protocol -// Copied here by aep 12/14/07 - - machine(Directory, "MESI Two Level directory protocol") : DirectoryMemory * directory; MemoryControl * memBuffer; Cycles to_mem_ctrl_latency := 1; Cycles directory_latency := 6; -{ - MessageBuffer requestToDir, network="From", virtual_network="0", + + MessageBuffer * requestToDir, network="From", virtual_network="0", ordered="false", vnet_type="request"; - MessageBuffer responseToDir, network="From", virtual_network="1", + MessageBuffer * responseToDir, network="From", virtual_network="1", ordered="false", vnet_type="response"; - MessageBuffer responseFromDir, network="To", virtual_network="1", + MessageBuffer * responseFromDir, network="To", virtual_network="1", ordered="false", vnet_type="response"; - +{ // STATES state_declaration(State, desc="Directory states", default="Directory_State_I") { // Base states diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm index 80c70c80a..e31832620 100644 --- a/src/mem/protocol/MESI_Two_Level-dma.sm +++ b/src/mem/protocol/MESI_Two_Level-dma.sm @@ -30,11 +30,12 @@ machine(DMA, "DMA Controller") : DMASequencer * dma_sequencer; Cycles request_latency := 6; -{ - - MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response"; - MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request"; + MessageBuffer * responseFromDir, network="From", virtual_network="1", + ordered="true", vnet_type="response"; + MessageBuffer * requestToDir, network="To", virtual_network="0", + ordered="false", vnet_type="request"; +{ state_declaration(State, desc="DMA states", default="DMA_State_READY") { READY, AccessPermission:Invalid, desc="Ready to accept a new request"; BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request"; @@ -74,7 +75,7 @@ machine(DMA, "DMA Controller") error("DMA does not support get data block."); } - out_port(reqToDirectory_out, RequestMsg, reqToDirectory, desc="..."); + out_port(requestToDir_out, RequestMsg, requestToDir, desc="..."); in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") { if (dmaRequestQueue_in.isReady()) { @@ -106,7 +107,7 @@ machine(DMA, "DMA Controller") action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, RequestMsg, request_latency) { + enqueue(requestToDir_out, RequestMsg, request_latency) { out_msg.Addr := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_READ; out_msg.DataBlk := in_msg.DataBlk; @@ -119,7 +120,7 @@ machine(DMA, "DMA Controller") action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, RequestMsg, request_latency) { + enqueue(requestToDir_out, RequestMsg, request_latency) { out_msg.Addr := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_WRITE; out_msg.DataBlk := in_msg.DataBlk; diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index 9b0c18bc8..ee774f4c2 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -28,20 +28,23 @@ */ machine(L1Cache, "MI Example L1 Cache") -: Sequencer * sequencer; - CacheMemory * cacheMemory; - Cycles cache_response_latency := 12; - Cycles issue_latency := 2; - bool send_evictions; + : Sequencer * sequencer; + CacheMemory * cacheMemory; + Cycles cache_response_latency := 12; + Cycles issue_latency := 2; + bool send_evictions; + + // NETWORK BUFFERS + MessageBuffer * requestFromCache, network="To", virtual_network="2", + ordered="true", vnet_type="request"; + MessageBuffer * responseFromCache, network="To", virtual_network="4", + ordered="true", vnet_type="response"; + + MessageBuffer * forwardToCache, network="From", virtual_network="3", + ordered="true", vnet_type="forward"; + MessageBuffer * responseToCache, network="From", virtual_network="4", + ordered="true", vnet_type="response"; { - - // NETWORK BUFFERS - MessageBuffer requestFromCache, network="To", virtual_network="2", ordered="true", vnet_type="request"; - MessageBuffer responseFromCache, network="To", virtual_network="4", ordered="true", vnet_type="response"; - - MessageBuffer forwardToCache, network="From", virtual_network="3", ordered="true", vnet_type="forward"; - MessageBuffer responseToCache, network="From", virtual_network="4", ordered="true", vnet_type="response"; - // STATES state_declaration(State, desc="Cache states") { I, AccessPermission:Invalid, desc="Not Present/Invalid"; diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm index f0d85cba8..cd12e3eb7 100644 --- a/src/mem/protocol/MI_example-dir.sm +++ b/src/mem/protocol/MI_example-dir.sm @@ -28,18 +28,22 @@ */ machine(Directory, "Directory protocol") -: DirectoryMemory * directory; - MemoryControl * memBuffer; - Cycles directory_latency := 12; + : DirectoryMemory * directory; + MemoryControl * memBuffer; + Cycles directory_latency := 12; + + MessageBuffer * forwardFromDir, network="To", virtual_network="3", + ordered="false", vnet_type="forward"; + MessageBuffer * responseFromDir, network="To", virtual_network="4", + ordered="false", vnet_type="response"; + MessageBuffer * dmaResponseFromDir, network="To", virtual_network="1", + ordered="true", vnet_type="response"; + + MessageBuffer * requestToDir, network="From", virtual_network="2", + ordered="true", vnet_type="request"; + MessageBuffer * dmaRequestToDir, network="From", virtual_network="0", + ordered="true", vnet_type="request"; { - - MessageBuffer forwardFromDir, network="To", virtual_network="3", ordered="false", vnet_type="forward"; - MessageBuffer responseFromDir, network="To", virtual_network="4", ordered="false", vnet_type="response"; - MessageBuffer dmaResponseFromDir, network="To", virtual_network="1", ordered="true", vnet_type="response"; - - MessageBuffer requestToDir, network="From", virtual_network="2", ordered="true", vnet_type="request"; - MessageBuffer dmaRequestToDir, network="From", virtual_network="0", ordered="true", vnet_type="request"; - // STATES state_declaration(State, desc="Directory states", default="Directory_State_I") { // Base states diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm index 14b8c4e4a..e328d9e20 100644 --- a/src/mem/protocol/MI_example-dma.sm +++ b/src/mem/protocol/MI_example-dma.sm @@ -28,13 +28,14 @@ */ machine(DMA, "DMA Controller") -: DMASequencer * dma_sequencer; - Cycles request_latency := 6; -{ - - MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response"; - MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request"; + : DMASequencer * dma_sequencer; + Cycles request_latency := 6; + MessageBuffer * responseFromDir, network="From", virtual_network="1", + ordered="true", vnet_type="response"; + MessageBuffer * requestToDir, network="To", virtual_network="0", + ordered="false", vnet_type="request"; +{ state_declaration(State, desc="DMA states", default="DMA_State_READY") { READY, AccessPermission:Invalid, desc="Ready to accept a new request"; BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request"; @@ -69,7 +70,7 @@ machine(DMA, "DMA Controller") error("DMA Controller does not support getDataBlock function.\n"); } - out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="..."); + out_port(requestToDir_out, DMARequestMsg, requestToDir, desc="..."); in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") { if (dmaRequestQueue_in.isReady()) { @@ -101,7 +102,7 @@ machine(DMA, "DMA Controller") action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, DMARequestMsg, request_latency) { + enqueue(requestToDir_out, DMARequestMsg, request_latency) { out_msg.PhysicalAddress := in_msg.PhysicalAddress; out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:READ; @@ -116,7 +117,7 @@ machine(DMA, "DMA Controller") action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, DMARequestMsg, request_latency) { + enqueue(requestToDir_out, DMARequestMsg, request_latency) { out_msg.PhysicalAddress := in_msg.PhysicalAddress; out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:WRITE; diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index fb74a67e4..3cd87616f 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -34,25 +34,24 @@ machine(L1Cache, "Directory protocol") Cycles request_latency := 2; Cycles use_timeout_latency := 50; bool send_evictions; -{ - - // NODE L1 CACHE - // From this node's L1 cache TO the network - // a local L1 -> this L2 bank, currently ordered with directory forwarded requests - MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false", vnet_type="request"; - // a local L1 -> this L2 bank - MessageBuffer responseFromL1Cache, network="To", virtual_network="2", ordered="false", vnet_type="response"; -// MessageBuffer writebackFromL1Cache, network="To", virtual_network="3", ordered="false", vnet_type="writeback"; - - - // To this node's L1 cache FROM the network - // a L2 bank -> this L1 - MessageBuffer requestToL1Cache, network="From", virtual_network="0", ordered="false", vnet_type="request"; - // a L2 bank -> this L1 - MessageBuffer responseToL1Cache, network="From", virtual_network="2", ordered="false", vnet_type="response"; - - + // Message Queues + // From this node's L1 cache TO the network + // a local L1 -> this L2 bank, currently ordered with directory forwarded requests + MessageBuffer * requestFromL1Cache, network="To", virtual_network="0", + ordered="false", vnet_type="request"; + // a local L1 -> this L2 bank + MessageBuffer * responseFromL1Cache, network="To", virtual_network="2", + ordered="false", vnet_type="response"; + + // To this node's L1 cache FROM the network + // a L2 bank -> this L1 + MessageBuffer * requestToL1Cache, network="From", virtual_network="0", + ordered="false", vnet_type="request"; + // a L2 bank -> this L1 + MessageBuffer * responseToL1Cache, network="From", virtual_network="2", + ordered="false", vnet_type="response"; +{ // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { // Base states diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm index 7d81f4164..46fd12a3a 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm @@ -30,20 +30,25 @@ machine(L2Cache, "Token protocol") : CacheMemory * L2cache; Cycles response_latency := 2; Cycles request_latency := 2; -{ // L2 BANK QUEUES // From local bank of L2 cache TO the network - MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="0", ordered="false", vnet_type="request"; // this L2 bank -> a local L1 - MessageBuffer GlobalRequestFromL2Cache, network="To", virtual_network="1", ordered="false", vnet_type="request"; // this L2 bank -> mod-directory - MessageBuffer responseFromL2Cache, network="To", virtual_network="2", ordered="false", vnet_type="response"; // this L2 bank -> a local L1 || mod-directory + MessageBuffer * L1RequestFromL2Cache, network="To", virtual_network="0", + ordered="false", vnet_type="request"; // this L2 bank -> a local L1 + MessageBuffer * GlobalRequestFromL2Cache, network="To", virtual_network="1", + ordered="false", vnet_type="request"; // this L2 bank -> mod-directory + MessageBuffer * responseFromL2Cache, network="To", virtual_network="2", + ordered="false", vnet_type="response"; // this L2 bank -> a local L1 || mod-directory // FROM the network to this local bank of L2 cache - MessageBuffer L1RequestToL2Cache, network="From", virtual_network="0", ordered="false", vnet_type="request"; // a local L1 -> this L2 bank, Lets try this??? - MessageBuffer GlobalRequestToL2Cache, network="From", virtual_network="1", ordered="false", vnet_type="request"; // mod-directory -> this L2 bank - MessageBuffer responseToL2Cache, network="From", virtual_network="2", ordered="false", vnet_type="response"; // a local L1 || mod-directory -> this L2 bank -// MessageBuffer L1WritebackToL2Cache, network="From", virtual_network="3", ordered="false", vnet_type="writeback"; + MessageBuffer * L1RequestToL2Cache, network="From", virtual_network="0", + ordered="false", vnet_type="request"; // a local L1 -> this L2 bank, Lets try this??? + MessageBuffer * GlobalRequestToL2Cache, network="From", virtual_network="1", + ordered="false", vnet_type="request"; // mod-directory -> this L2 bank + MessageBuffer * responseToL2Cache, network="From", virtual_network="2", + ordered="false", vnet_type="response"; // a local L1 || mod-directory -> this L2 bank +{ // STATES state_declaration(State, desc="L2 Cache states", default="L2Cache_State_I") { diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm index b403bc91c..272a8c9ab 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm @@ -30,16 +30,19 @@ machine(Directory, "Directory protocol") : DirectoryMemory * directory; MemoryControl * memBuffer; Cycles directory_latency := 6; -{ - - // ** IN QUEUES ** - MessageBuffer requestToDir, network="From", virtual_network="1", ordered="false", vnet_type="request"; // a mod-L2 bank -> this Dir - MessageBuffer responseToDir, network="From", virtual_network="2", ordered="false", vnet_type="response"; // a mod-L2 bank -> this Dir - MessageBuffer forwardFromDir, network="To", virtual_network="1", ordered="false", vnet_type="forward"; - MessageBuffer responseFromDir, network="To", virtual_network="2", ordered="false", vnet_type="response"; // Dir -> mod-L2 bank + // Message Queues + MessageBuffer * requestToDir, network="From", virtual_network="1", + ordered="false", vnet_type="request"; // a mod-L2 bank -> this Dir + MessageBuffer * responseToDir, network="From", virtual_network="2", + ordered="false", vnet_type="response"; // a mod-L2 bank -> this Dir + MessageBuffer * forwardFromDir, network="To", virtual_network="1", + ordered="false", vnet_type="forward"; + MessageBuffer * responseFromDir, network="To", virtual_network="2", + ordered="false", vnet_type="response"; // Dir -> mod-L2 bank +{ // STATES state_declaration(State, desc="Directory states", default="Directory_State_I") { // Base states diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm index 1a8b3aea9..767a51a1f 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -27,22 +27,26 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -machine(DMA, "DMA Controller") -: DMASequencer * dma_sequencer; - Cycles request_latency := 14; - Cycles response_latency := 14; -{ - MessageBuffer responseFromDir, network="From", virtual_network="2", ordered="false", vnet_type="response"; +machine(DMA, "DMA Controller") + : DMASequencer * dma_sequencer; + Cycles request_latency := 14; + Cycles response_latency := 14; + + MessageBuffer * responseFromDir, network="From", virtual_network="2", + ordered="false", vnet_type="response"; + + MessageBuffer * reqToDir, network="To", virtual_network="1", + ordered="false", vnet_type="request"; + MessageBuffer * respToDir, network="To", virtual_network="2", + ordered="false", vnet_type="dmaresponse"; - MessageBuffer reqToDir, network="To", virtual_network="1", ordered="false", vnet_type="request"; - MessageBuffer respToDir, network="To", virtual_network="2", ordered="false", vnet_type="dmaresponse"; - +{ state_declaration(State, desc="DMA states", default="DMA_State_READY") { READY, AccessPermission:Invalid, desc="Ready to accept a new request"; BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request"; BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request"; } - + enumeration(Event, desc="DMA events") { ReadRequest, desc="A new read request"; WriteRequest, desc="A new write request"; @@ -293,7 +297,7 @@ machine(DMA, "DMA Controller") } transition(BUSY_WR, All_Acks, READY) { - a_ackCallback; + a_ackCallback; u_sendExclusiveUnblockToDir; w_deallocateTBE; p_popTriggerQueue; diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm index b1197780f..860744384 100644 --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm @@ -48,24 +48,32 @@ machine(L1Cache, "Token protocol") bool dynamic_timeout_enabled := "True"; bool no_mig_atomic := "True"; bool send_evictions; -{ - - // From this node's L1 cache TO the network - - // a local L1 -> this L2 bank - MessageBuffer responseFromL1Cache, network="To", virtual_network="4", ordered="false", vnet_type="response"; - MessageBuffer persistentFromL1Cache, network="To", virtual_network="3", ordered="true", vnet_type="persistent"; - // a local L1 -> this L2 bank, currently ordered with directory forwarded requests - MessageBuffer requestFromL1Cache, network="To", virtual_network="1", ordered="false", vnet_type="request"; + // Message Queues + // From this node's L1 cache TO the network + + // a local L1 -> this L2 bank + MessageBuffer * responseFromL1Cache, network="To", virtual_network="4", + ordered="false", vnet_type="response"; + MessageBuffer * persistentFromL1Cache, network="To", virtual_network="3", + ordered="true", vnet_type="persistent"; + // a local L1 -> this L2 bank, currently ordered with directory forwarded requests + MessageBuffer * requestFromL1Cache, network="To", virtual_network="1", + ordered="false", vnet_type="request"; + + + // To this node's L1 cache FROM the network + + // a L2 bank -> this L1 + MessageBuffer * responseToL1Cache, network="From", virtual_network="4", + ordered="false", vnet_type="response"; + MessageBuffer * persistentToL1Cache, network="From", virtual_network="3", + ordered="true", vnet_type="persistent"; + // a L2 bank -> this L1 + MessageBuffer * requestToL1Cache, network="From", virtual_network="1", + ordered="false", vnet_type="request"; - // To this node's L1 cache FROM the network - // a L2 bank -> this L1 - MessageBuffer responseToL1Cache, network="From", virtual_network="4", ordered="false", vnet_type="response"; - MessageBuffer persistentToL1Cache, network="From", virtual_network="3", ordered="true", vnet_type="persistent"; - // a L2 bank -> this L1 - MessageBuffer requestToL1Cache, network="From", virtual_network="1", ordered="false", vnet_type="request"; - +{ // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { // Base states diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm index f8bd01695..a2488066a 100644 --- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm @@ -32,29 +32,36 @@ machine(L2Cache, "Token protocol") Cycles l2_request_latency := 5; Cycles l2_response_latency := 5; bool filtering_enabled := "True"; -{ - - // L2 BANK QUEUES - // From local bank of L2 cache TO the network - - // this L2 bank -> a local L1 || mod-directory - MessageBuffer responseFromL2Cache, network="To", virtual_network="4", ordered="false", vnet_type="response"; - // this L2 bank -> mod-directory - MessageBuffer GlobalRequestFromL2Cache, network="To", virtual_network="2", ordered="false", vnet_type="request"; - // this L2 bank -> a local L1 - MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="1", ordered="false", vnet_type="request"; + // L2 BANK QUEUES + // From local bank of L2 cache TO the network + + // this L2 bank -> a local L1 || mod-directory + MessageBuffer * responseFromL2Cache, network="To", virtual_network="4", + ordered="false", vnet_type="response"; + // this L2 bank -> mod-directory + MessageBuffer * GlobalRequestFromL2Cache, network="To", virtual_network="2", + ordered="false", vnet_type="request"; + // this L2 bank -> a local L1 + MessageBuffer * L1RequestFromL2Cache, network="To", virtual_network="1", + ordered="false", vnet_type="request"; + + + // FROM the network to this local bank of L2 cache + + // a local L1 || mod-directory -> this L2 bank + MessageBuffer * responseToL2Cache, network="From", virtual_network="4", + ordered="false", vnet_type="response"; + MessageBuffer * persistentToL2Cache, network="From", virtual_network="3", + ordered="true", vnet_type="persistent"; + // mod-directory -> this L2 bank + MessageBuffer * GlobalRequestToL2Cache, network="From", virtual_network="2", + ordered="false", vnet_type="request"; + // a local L1 -> this L2 bank + MessageBuffer * L1RequestToL2Cache, network="From", virtual_network="1", + ordered="false", vnet_type="request"; - // FROM the network to this local bank of L2 cache - - // a local L1 || mod-directory -> this L2 bank - MessageBuffer responseToL2Cache, network="From", virtual_network="4", ordered="false", vnet_type="response"; - MessageBuffer persistentToL2Cache, network="From", virtual_network="3", ordered="true", vnet_type="persistent"; - // mod-directory -> this L2 bank - MessageBuffer GlobalRequestToL2Cache, network="From", virtual_network="2", ordered="false", vnet_type="request"; - // a local L1 -> this L2 bank - MessageBuffer L1RequestToL2Cache, network="From", virtual_network="1", ordered="false", vnet_type="request"; - +{ // STATES state_declaration(State, desc="L2 Cache states", default="L2Cache_State_I") { // Base states diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm index 5cb29fcc2..be5df02e0 100644 --- a/src/mem/protocol/MOESI_CMP_token-dir.sm +++ b/src/mem/protocol/MOESI_CMP_token-dir.sm @@ -34,18 +34,34 @@ machine(Directory, "Token protocol") bool distributed_persistent := "True"; Cycles fixed_timeout_latency := 100; Cycles reissue_wakeup_latency := 10; -{ - MessageBuffer dmaResponseFromDir, network="To", virtual_network="5", ordered="true", vnet_type="response"; - MessageBuffer responseFromDir, network="To", virtual_network="4", ordered="false", vnet_type="response"; - MessageBuffer persistentFromDir, network="To", virtual_network="3", ordered="true", vnet_type="persistent"; - MessageBuffer requestFromDir, network="To", virtual_network="1", ordered="false", vnet_type="request"; + // Message Queues from dir to other controllers / network + MessageBuffer * dmaResponseFromDir, network="To", virtual_network="5", + ordered="true", vnet_type="response"; + + MessageBuffer * responseFromDir, network="To", virtual_network="4", + ordered="false", vnet_type="response"; + + MessageBuffer * persistentFromDir, network="To", virtual_network="3", + ordered="true", vnet_type="persistent"; - MessageBuffer responseToDir, network="From", virtual_network="4", ordered="false", vnet_type="response"; - MessageBuffer persistentToDir, network="From", virtual_network="3", ordered="true", vnet_type="persistent"; - MessageBuffer requestToDir, network="From", virtual_network="2", ordered="false", vnet_type="request"; - MessageBuffer dmaRequestToDir, network="From", virtual_network="0", ordered="true", vnet_type="request"; + MessageBuffer * requestFromDir, network="To", virtual_network="1", + ordered="false", vnet_type="request"; + + // Message Queues to dir from other controllers / network + MessageBuffer * responseToDir, network="From", virtual_network="4", + ordered="false", vnet_type="response"; + MessageBuffer * persistentToDir, network="From", virtual_network="3", + ordered="true", vnet_type="persistent"; + + MessageBuffer * requestToDir, network="From", virtual_network="2", + ordered="false", vnet_type="request"; + + MessageBuffer * dmaRequestToDir, network="From", virtual_network="0", + ordered="true", vnet_type="request"; + +{ // STATES state_declaration(State, desc="Directory states", default="Directory_State_O") { // Base states diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm index 441a001fc..72b0e52a5 100644 --- a/src/mem/protocol/MOESI_CMP_token-dma.sm +++ b/src/mem/protocol/MOESI_CMP_token-dma.sm @@ -28,13 +28,16 @@ machine(DMA, "DMA Controller") -: DMASequencer * dma_sequencer; - Cycles request_latency := 6; -{ + : DMASequencer * dma_sequencer; + Cycles request_latency := 6; - MessageBuffer responseFromDir, network="From", virtual_network="5", ordered="true", vnet_type="response"; - MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request"; + // Messsage Queues + MessageBuffer * responseFromDir, network="From", virtual_network="5", + ordered="true", vnet_type="response"; + MessageBuffer * reqToDirectory, network="To", virtual_network="0", + ordered="false", vnet_type="request"; +{ state_declaration(State, desc="DMA states", default="DMA_State_READY") { READY, AccessPermission:Invalid, desc="Ready to accept a new request"; BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request"; diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index 7c150bda0..de502e118 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -34,26 +34,29 @@ */ machine({L1Cache, L2Cache}, "AMD Hammer-like protocol") -: Sequencer * sequencer; - CacheMemory * L1Icache; - CacheMemory * L1Dcache; - CacheMemory * L2cache; - Cycles cache_response_latency := 10; - Cycles issue_latency := 2; - Cycles l2_cache_hit_latency := 10; - bool no_mig_atomic := "True"; - bool send_evictions; + : Sequencer * sequencer; + CacheMemory * L1Icache; + CacheMemory * L1Dcache; + CacheMemory * L2cache; + Cycles cache_response_latency := 10; + Cycles issue_latency := 2; + Cycles l2_cache_hit_latency := 10; + bool no_mig_atomic := "True"; + bool send_evictions; + + // NETWORK BUFFERS + MessageBuffer * requestFromCache, network="To", virtual_network="2", + ordered="false", vnet_type="request"; + MessageBuffer * responseFromCache, network="To", virtual_network="4", + ordered="false", vnet_type="response"; + MessageBuffer * unblockFromCache, network="To", virtual_network="5", + ordered="false", vnet_type="unblock"; + + MessageBuffer * forwardToCache, network="From", virtual_network="3", + ordered="false", vnet_type="forward"; + MessageBuffer * responseToCache, network="From", virtual_network="4", + ordered="false", vnet_type="response"; { - - // NETWORK BUFFERS - MessageBuffer requestFromCache, network="To", virtual_network="2", ordered="false", vnet_type="request"; - MessageBuffer responseFromCache, network="To", virtual_network="4", ordered="false", vnet_type="response"; - MessageBuffer unblockFromCache, network="To", virtual_network="5", ordered="false", vnet_type="unblock"; - - MessageBuffer forwardToCache, network="From", virtual_network="3", ordered="false", vnet_type="forward"; - MessageBuffer responseToCache, network="From", virtual_network="4", ordered="false", vnet_type="response"; - - // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { // Base states diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm index 4e2f846e2..db11b290f 100644 --- a/src/mem/protocol/MOESI_hammer-dir.sm +++ b/src/mem/protocol/MOESI_hammer-dir.sm @@ -34,28 +34,37 @@ */ machine(Directory, "AMD Hammer-like protocol") -: DirectoryMemory * directory; - CacheMemory * probeFilter; - MemoryControl * memBuffer; - Cycles memory_controller_latency := 2; - bool probe_filter_enabled := "False"; - bool full_bit_dir_enabled := "False"; -{ + : DirectoryMemory * directory; + CacheMemory * probeFilter; + MemoryControl * memBuffer; + Cycles memory_controller_latency := 2; + bool probe_filter_enabled := "False"; + bool full_bit_dir_enabled := "False"; - MessageBuffer forwardFromDir, network="To", virtual_network="3", ordered="false", vnet_type="forward"; - MessageBuffer responseFromDir, network="To", virtual_network="4", ordered="false", vnet_type="response"; - // - // For a finite buffered network, note that the DMA response network only - // works at this relatively lower numbered (lower priority) virtual network - // because the trigger queue decouples cache responses from DMA responses. - // - MessageBuffer dmaResponseFromDir, network="To", virtual_network="1", ordered="true", vnet_type="response"; + MessageBuffer * forwardFromDir, network="To", virtual_network="3", + ordered="false", vnet_type="forward"; + + MessageBuffer * responseFromDir, network="To", virtual_network="4", + ordered="false", vnet_type="response"; - MessageBuffer unblockToDir, network="From", virtual_network="5", ordered="false", vnet_type="unblock"; - MessageBuffer responseToDir, network="From", virtual_network="4", ordered="false", vnet_type="response"; - MessageBuffer requestToDir, network="From", virtual_network="2", ordered="false", vnet_type="request", recycle_latency="1"; - MessageBuffer dmaRequestToDir, network="From", virtual_network="0", ordered="true", vnet_type="request"; + // For a finite buffered network, note that the DMA response network only + // works at this relatively lower numbered (lower priority) virtual network + // because the trigger queue decouples cache responses from DMA responses. + MessageBuffer * dmaResponseFromDir, network="To", virtual_network="1", + ordered="true", vnet_type="response"; + MessageBuffer * unblockToDir, network="From", virtual_network="5", + ordered="false", vnet_type="unblock"; + + MessageBuffer * responseToDir, network="From", virtual_network="4", + ordered="false", vnet_type="response"; + + MessageBuffer * requestToDir, network="From", virtual_network="2", + ordered="false", vnet_type="request", recycle_latency="1"; + + MessageBuffer * dmaRequestToDir, network="From", virtual_network="0", + ordered="true", vnet_type="request"; +{ // STATES state_declaration(State, desc="Directory states", default="Directory_State_E") { // Base states diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/protocol/MOESI_hammer-dma.sm index e4d26bb48..ab41adb4d 100644 --- a/src/mem/protocol/MOESI_hammer-dma.sm +++ b/src/mem/protocol/MOESI_hammer-dma.sm @@ -28,16 +28,15 @@ machine(DMA, "DMA Controller") -: DMASequencer * dma_sequencer; - Cycles request_latency := 6; -{ - - MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response"; - MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", vnet_type="request"; + : DMASequencer * dma_sequencer; + Cycles request_latency := 6; - state_declaration(State, - desc="DMA states", - default="DMA_State_READY") { + MessageBuffer * responseFromDir, network="From", virtual_network="1", + ordered="true", vnet_type="response"; + MessageBuffer * requestToDir, network="To", virtual_network="0", + ordered="false", vnet_type="request"; +{ + state_declaration(State, desc="DMA states", default="DMA_State_READY") { READY, AccessPermission:Invalid, desc="Ready to accept a new request"; BUSY_RD, AccessPermission:Busy, desc="Busy: currently processing a request"; BUSY_WR, AccessPermission:Busy, desc="Busy: currently processing a request"; @@ -71,7 +70,7 @@ machine(DMA, "DMA Controller") error("DMA Controller does not support getDataBlock function.\n"); } - out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="..."); + out_port(requestToDir_out, DMARequestMsg, requestToDir, desc="..."); in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") { if (dmaRequestQueue_in.isReady()) { @@ -103,7 +102,7 @@ machine(DMA, "DMA Controller") action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, DMARequestMsg, request_latency) { + enqueue(requestToDir_out, DMARequestMsg, request_latency) { out_msg.PhysicalAddress := in_msg.PhysicalAddress; out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:READ; @@ -118,7 +117,7 @@ machine(DMA, "DMA Controller") action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, DMARequestMsg, request_latency) { + enqueue(requestToDir_out, DMARequestMsg, request_latency) { out_msg.PhysicalAddress := in_msg.PhysicalAddress; out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:WRITE; diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm index f69aecd93..e0307152d 100644 --- a/src/mem/protocol/Network_test-cache.sm +++ b/src/mem/protocol/Network_test-cache.sm @@ -32,15 +32,17 @@ machine(L1Cache, "Network_test L1 Cache") -: Sequencer * sequencer; - Cycles issue_latency := 2; + : Sequencer * sequencer; + Cycles issue_latency := 2; + + // NETWORK BUFFERS + MessageBuffer * requestFromCache, network="To", virtual_network="0", + ordered="false", vnet_type = "request"; + MessageBuffer * forwardFromCache, network="To", virtual_network="1", + ordered="false", vnet_type = "forward"; + MessageBuffer * responseFromCache, network="To", virtual_network="2", + ordered="false", vnet_type = "response"; { - - // NETWORK BUFFERS - MessageBuffer requestFromCache, network="To", virtual_network="0", ordered="false", vnet_type = "request"; - MessageBuffer forwardFromCache, network="To", virtual_network="1", ordered="false", vnet_type = "forward"; - MessageBuffer responseFromCache, network="To", virtual_network="2", ordered="false", vnet_type = "response"; - // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { I, AccessPermission:Invalid, desc="Not Present/Invalid"; diff --git a/src/mem/protocol/Network_test-dir.sm b/src/mem/protocol/Network_test-dir.sm index 47e248dff..4d6472c54 100644 --- a/src/mem/protocol/Network_test-dir.sm +++ b/src/mem/protocol/Network_test-dir.sm @@ -32,13 +32,13 @@ machine(Directory, "Network_test Directory") -: + : MessageBuffer * requestToDir, network="From", virtual_network="0", + ordered="false", vnet_type = "request"; + MessageBuffer * forwardToDir, network="From", virtual_network="1", + ordered="false", vnet_type = "forward"; + MessageBuffer * responseToDir, network="From", virtual_network="2", + ordered="false", vnet_type = "response"; { - - MessageBuffer requestToDir, network="From", virtual_network="0", ordered="false", vnet_type = "request"; - MessageBuffer forwardToDir, network="From", virtual_network="1", ordered="false", vnet_type = "forward"; - MessageBuffer responseToDir, network="From", virtual_network="2", ordered="false", vnet_type = "response"; - // STATES state_declaration(State, desc="Directory states", default="Directory_State_I") { // Base states |