diff options
Diffstat (limited to 'src/mem/protocol')
22 files changed, 57 insertions, 49 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm index bcfb20297..113421842 100644 --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm @@ -33,9 +33,9 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") CacheMemory * L1DcacheMemory, Prefetcher * prefetcher = 'NULL', int l2_select_num_bits, - int l1_request_latency = 2, - int l1_response_latency = 2, - int to_l2_latency = 1, + Cycles l1_request_latency = 2, + Cycles l1_response_latency = 2, + Cycles to_l2_latency = 1, bool send_evictions, bool enable_prefetch = "False" { diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm index 849714c49..645b2d94c 100644 --- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm @@ -34,9 +34,9 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") : CacheMemory * L2cacheMemory, - int l2_request_latency = 2, - int l2_response_latency = 2, - int to_l1_latency = 1 + Cycles l2_request_latency = 2, + Cycles l2_response_latency = 2, + Cycles to_l1_latency = 1 { // L2 BANK QUEUES // From local bank of L2 cache TO the network diff --git a/src/mem/protocol/MESI_CMP_directory-dir.sm b/src/mem/protocol/MESI_CMP_directory-dir.sm index 0dbbafafa..38054136d 100644 --- a/src/mem/protocol/MESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MESI_CMP_directory-dir.sm @@ -38,8 +38,8 @@ machine(Directory, "MESI_CMP_filter_directory protocol") : DirectoryMemory * directory, MemoryControl * memBuffer, - int to_mem_ctrl_latency = 1, - int directory_latency = 6 + Cycles to_mem_ctrl_latency = 1, + Cycles directory_latency = 6 { MessageBuffer requestToDir, network="From", virtual_network="0", ordered="false", vnet_type="request"; diff --git a/src/mem/protocol/MESI_CMP_directory-dma.sm b/src/mem/protocol/MESI_CMP_directory-dma.sm index 374463164..2f8d9d4f2 100644 --- a/src/mem/protocol/MESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MESI_CMP_directory-dma.sm @@ -29,7 +29,7 @@ machine(DMA, "DMA Controller") : DMASequencer * dma_sequencer, - int request_latency = 6 + Cycles request_latency = 6 { MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true"; diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index 91f060a38..e62317efa 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -30,8 +30,8 @@ machine(L1Cache, "MI Example L1 Cache") : Sequencer * sequencer, CacheMemory * cacheMemory, - int cache_response_latency = 12, - int issue_latency = 2, + Cycles cache_response_latency = 12, + Cycles issue_latency = 2, bool send_evictions { diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm index edb571c1f..e1fd53594 100644 --- a/src/mem/protocol/MI_example-dir.sm +++ b/src/mem/protocol/MI_example-dir.sm @@ -30,7 +30,7 @@ machine(Directory, "Directory protocol") : DirectoryMemory * directory, MemoryControl * memBuffer, - int directory_latency = 12 + Cycles directory_latency = 12 { MessageBuffer forwardFromDir, network="To", virtual_network="3", ordered="false", vnet_type="forward"; diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm index c7c576a2c..5d67da465 100644 --- a/src/mem/protocol/MI_example-dma.sm +++ b/src/mem/protocol/MI_example-dma.sm @@ -29,7 +29,7 @@ machine(DMA, "DMA Controller") : DMASequencer * dma_sequencer, - int request_latency = 6 + Cycles request_latency = 6 { MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true"; diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index f6ed32009..101b7abd6 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -37,7 +37,8 @@ machine(L1Cache, "Directory protocol") CacheMemory * L1IcacheMemory, CacheMemory * L1DcacheMemory, int l2_select_num_bits, - int request_latency = 2, + Cycles request_latency = 2, + Cycles use_timeout_latency = 50, bool send_evictions { @@ -696,7 +697,7 @@ machine(L1Cache, "Directory protocol") } action(o_scheduleUseTimeout, "oo", desc="Schedule a use timeout.") { - useTimerTable.set(address, 50); + useTimerTable.set(address, use_timeout_latency); } action(ub_dmaUnblockL2Cache, "ub", desc="Send dma ack to l2 cache") { diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm index ba78cff9f..6c61d3eb6 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm @@ -34,8 +34,8 @@ machine(L2Cache, "Token protocol") : CacheMemory * L2cacheMemory, - int response_latency = 2, - int request_latency = 2 + Cycles response_latency = 2, + Cycles request_latency = 2 { // L2 BANK QUEUES diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm index f458fccd8..57ef10ae1 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm @@ -33,7 +33,7 @@ machine(Directory, "Directory protocol") : DirectoryMemory * directory, MemoryControl * memBuffer, - int directory_latency = 6 + Cycles directory_latency = 6 { // ** IN QUEUES ** diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm index 6d10305ea..18ab25f65 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -1,8 +1,8 @@ machine(DMA, "DMA Controller") : DMASequencer * dma_sequencer, - int request_latency = 14, - int response_latency = 14 + Cycles request_latency = 14, + Cycles response_latency = 14 { MessageBuffer responseFromDir, network="From", virtual_network="2", ordered="false", vnet_type="response"; diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm index 5533a34dc..365a963b9 100644 --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm @@ -38,10 +38,14 @@ machine(L1Cache, "Token protocol") CacheMemory * L1DcacheMemory, int l2_select_num_bits, int N_tokens, - int l1_request_latency = 2, - int l1_response_latency = 2, + + Cycles l1_request_latency = 2, + Cycles l1_response_latency = 2, int retry_threshold = 1, - int fixed_timeout_latency = 100, + Cycles fixed_timeout_latency = 100, + Cycles reissue_wakeup_latency = 10, + Cycles use_timeout_latency = 50, + bool dynamic_timeout_enabled = true, bool no_mig_atomic = true, bool send_evictions @@ -195,19 +199,20 @@ machine(L1Cache, "Token protocol") int outstandingRequests, default="0"; int outstandingPersistentRequests, default="0"; - int averageLatencyHysteresis, default="(8)"; // Constant that provides hysteresis for calculated the estimated average - int averageLatencyCounter, default="(500 << (*m_L1Cache_averageLatencyHysteresis_ptr))"; + // Constant that provides hysteresis for calculated the estimated average + int averageLatencyHysteresis, default="(8)"; + Cycles averageLatencyCounter, + default="(Cycles(500) << (*m_L1Cache_averageLatencyHysteresis_ptr))"; - int averageLatencyEstimate() { + Cycles averageLatencyEstimate() { DPRINTF(RubySlicc, "%d\n", (averageLatencyCounter >> averageLatencyHysteresis)); //profile_average_latency_estimate( (averageLatencyCounter >> averageLatencyHysteresis) ); return averageLatencyCounter >> averageLatencyHysteresis; } - void updateAverageLatencyEstimate(int latency) { + void updateAverageLatencyEstimate(Cycles latency) { DPRINTF(RubySlicc, "%d\n", latency); - assert(latency >= 0); // By subtracting the current average and then adding the most // recent sample, we calculate an estimate of the recent average. @@ -781,7 +786,7 @@ machine(L1Cache, "Token protocol") // IssueCount. // Set a wakeup timer - reissueTimerTable.set(address, 10); + reissueTimerTable.set(address, reissue_wakeup_latency); } } else { @@ -834,7 +839,7 @@ machine(L1Cache, "Token protocol") // Set a wakeup timer if (dynamic_timeout_enabled) { - reissueTimerTable.set(address, 1.25 * averageLatencyEstimate()); + reissueTimerTable.set(address, (5 * averageLatencyEstimate()) / 4); } else { reissueTimerTable.set(address, fixed_timeout_latency); } @@ -902,10 +907,9 @@ machine(L1Cache, "Token protocol") // IssueCount. // Set a wakeup timer - reissueTimerTable.set(address, 10); + reissueTimerTable.set(address, reissue_wakeup_latency); } - } else { // Make a normal request enqueue(requestNetwork_out, RequestMsg, latency = l1_request_latency) { @@ -961,7 +965,7 @@ machine(L1Cache, "Token protocol") // Set a wakeup timer if (dynamic_timeout_enabled) { - reissueTimerTable.set(address, 1.25 * averageLatencyEstimate()); + reissueTimerTable.set(address, (5 * averageLatencyEstimate()) / 4); } else { reissueTimerTable.set(address, fixed_timeout_latency); } @@ -1381,7 +1385,7 @@ machine(L1Cache, "Token protocol") } action(o_scheduleUseTimeout, "o", desc="Schedule a use timeout.") { - useTimerTable.set(address, 50); + useTimerTable.set(address, use_timeout_latency); } action(p_informL2AboutTokenLoss, "p", desc="Inform L2 about loss of all tokens") { @@ -1448,7 +1452,7 @@ machine(L1Cache, "Token protocol") // Update average latency if (tbe.IssueCount <= 1) { if (tbe.ExternalResponse == true) { - updateAverageLatencyEstimate(time_to_int(curCycle()) - time_to_int(tbe.IssueTime)); + updateAverageLatencyEstimate(TimeToCycles(curCycle() - tbe.IssueTime)); } } diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm index 411390a5e..da8bcc6fa 100644 --- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm @@ -35,8 +35,8 @@ machine(L2Cache, "Token protocol") : CacheMemory * L2cacheMemory, int N_tokens, - int l2_request_latency = 5, - int l2_response_latency = 5, + Cycles l2_request_latency = 5, + Cycles l2_response_latency = 5, bool filtering_enabled = true { diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm index 5a604555e..84e888d55 100644 --- a/src/mem/protocol/MOESI_CMP_token-dir.sm +++ b/src/mem/protocol/MOESI_CMP_token-dir.sm @@ -36,9 +36,10 @@ machine(Directory, "Token protocol") : DirectoryMemory * directory, MemoryControl * memBuffer, int l2_select_num_bits, - int directory_latency = 5, + Cycles directory_latency = 5, bool distributed_persistent = true, - int fixed_timeout_latency = 100 + Cycles fixed_timeout_latency = 100, + Cycles reissue_wakeup_latency = 10 { MessageBuffer dmaResponseFromDir, network="To", virtual_network="5", ordered="true", vnet_type="response"; @@ -470,7 +471,7 @@ machine(Directory, "Token protocol") // IssueCount. // Set a wakeup timer - reissueTimerTable.set(address, 10); + reissueTimerTable.set(address, reissue_wakeup_latency); } } @@ -540,7 +541,7 @@ machine(Directory, "Token protocol") // IssueCount. // Set a wakeup timer - reissueTimerTable.set(address, 10); + reissueTimerTable.set(address, reissue_wakeup_latency); } } diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm index 98666998a..637778fcf 100644 --- a/src/mem/protocol/MOESI_CMP_token-dma.sm +++ b/src/mem/protocol/MOESI_CMP_token-dma.sm @@ -29,7 +29,7 @@ machine(DMA, "DMA Controller") : DMASequencer * dma_sequencer, - int request_latency = 6 + Cycles request_latency = 6 { MessageBuffer responseFromDir, network="From", virtual_network="5", ordered="true", vnet_type="response", no_vector="true"; diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index e4d01df65..fc2a9da90 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -38,9 +38,9 @@ machine(L1Cache, "AMD Hammer-like protocol") CacheMemory * L1IcacheMemory, CacheMemory * L1DcacheMemory, CacheMemory * L2cacheMemory, - int cache_response_latency = 10, - int issue_latency = 2, - int l2_cache_hit_latency = 10, + Cycles cache_response_latency = 10, + Cycles issue_latency = 2, + Cycles l2_cache_hit_latency = 10, bool no_mig_atomic = true, bool send_evictions { diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm index f923ddeab..40f4db73e 100644 --- a/src/mem/protocol/MOESI_hammer-dir.sm +++ b/src/mem/protocol/MOESI_hammer-dir.sm @@ -37,7 +37,7 @@ machine(Directory, "AMD Hammer-like protocol") : DirectoryMemory * directory, CacheMemory * probeFilter, MemoryControl * memBuffer, - int memory_controller_latency = 2, + Cycles memory_controller_latency = 2, bool probe_filter_enabled = false, bool full_bit_dir_enabled = false { diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/protocol/MOESI_hammer-dma.sm index bfb3cb98d..fd7734677 100644 --- a/src/mem/protocol/MOESI_hammer-dma.sm +++ b/src/mem/protocol/MOESI_hammer-dma.sm @@ -29,7 +29,7 @@ machine(DMA, "DMA Controller") : DMASequencer * dma_sequencer, - int request_latency = 6 + Cycles request_latency = 6 { MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response", no_vector="true"; diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm index 1e49e1d7b..81e648783 100644 --- a/src/mem/protocol/Network_test-cache.sm +++ b/src/mem/protocol/Network_test-cache.sm @@ -33,7 +33,7 @@ machine(L1Cache, "Network_test L1 Cache") : Sequencer * sequencer, - int issue_latency = 2 + Cycles issue_latency = 2 { // NETWORK BUFFERS diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm index 6c8cfc832..8ca1ed32c 100644 --- a/src/mem/protocol/RubySlicc_Exports.sm +++ b/src/mem/protocol/RubySlicc_Exports.sm @@ -37,6 +37,7 @@ external_type(Time, primitive="yes", default="0"); external_type(PacketPtr, primitive="yes"); external_type(Packet, primitive="yes"); external_type(Address); +external_type(Cycles, primitive="yes"); structure(DataBlock, external = "yes", desc="..."){ void clear(); diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm index b4601e9e6..0f6cd0b96 100644 --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -171,7 +171,7 @@ structure (DMASequencer, external = "yes") { structure (TimerTable, inport="yes", external = "yes") { bool isReady(); Address readyAddress(); - void set(Address, int); + void set(Address, Cycles); void unset(Address); bool isSet(Address); } diff --git a/src/mem/protocol/RubySlicc_Util.sm b/src/mem/protocol/RubySlicc_Util.sm index 65f47d5aa..238884503 100644 --- a/src/mem/protocol/RubySlicc_Util.sm +++ b/src/mem/protocol/RubySlicc_Util.sm @@ -33,6 +33,7 @@ void error(std::string msg); void assert(bool condition); int random(int number); Time zero_time(); +Cycles TimeToCycles(Time t); NodeID intToID(int nodenum); int IDToInt(NodeID id); int time_to_int(Time time); |