diff options
Diffstat (limited to 'src/mem/protocol')
-rw-r--r-- | src/mem/protocol/MESI_CMP_directory-L1cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MESI_CMP_directory-L2cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MESI_CMP_directory-dir.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MI_example-cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MI_example-dir.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 3 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-dir.sm | 3 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-dma.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_token-L1cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_token-dir.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_hammer-cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_hammer-dir.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/Network_test-cache.sm | 27 | ||||
-rw-r--r-- | src/mem/protocol/RubySlicc_Exports.sm | 1 |
15 files changed, 17 insertions, 39 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm index eb8e62d30..d12e44ba3 100644 --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm @@ -126,7 +126,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") bool isPresent(Address); } - TBETable L1_TBEs, template="<L1Cache_TBE>"; + TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; MessageBuffer mandatoryQueue, ordered="false"; diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm index fbdc10ac2..849714c49 100644 --- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm @@ -151,7 +151,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") bool isPresent(Address); } - TBETable L2_TBEs, template="<L2Cache_TBE>"; + TBETable L2_TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs"; void set_cache_entry(AbstractCacheEntry a); void unset_cache_entry(); diff --git a/src/mem/protocol/MESI_CMP_directory-dir.sm b/src/mem/protocol/MESI_CMP_directory-dir.sm index d98326b34..0dbbafafa 100644 --- a/src/mem/protocol/MESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MESI_CMP_directory-dir.sm @@ -105,7 +105,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") // ** OBJECTS ** - TBETable TBEs, template="<Directory_TBE>"; + TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs"; void set_tbe(TBE tbe); void unset_tbe(); diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index 5040eb85d..91f060a38 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -98,7 +98,7 @@ machine(L1Cache, "MI Example L1 Cache") // STRUCTURES - TBETable TBEs, template="<L1Cache_TBE>"; + TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; // PROTOTYPES void set_cache_entry(AbstractCacheEntry a); diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm index f15ccb14e..edb571c1f 100644 --- a/src/mem/protocol/MI_example-dir.sm +++ b/src/mem/protocol/MI_example-dir.sm @@ -102,7 +102,7 @@ machine(Directory, "Directory protocol") } // ** OBJECTS ** - TBETable TBEs, template="<Directory_TBE>"; + TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs"; void set_tbe(TBE b); void unset_tbe(); diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index 6295f90fd..f6ed32009 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -142,7 +142,7 @@ machine(L1Cache, "Directory protocol") MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true"; - TBETable TBEs, template="<L1Cache_TBE>"; + TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; TimerTable useTimerTable; int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm index 2e4e66a7b..ba78cff9f 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm @@ -224,8 +224,7 @@ machine(L2Cache, "Token protocol") bool isTagPresent(Address); } - - TBETable TBEs, template="<L2Cache_TBE>"; + TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs"; PerfectCacheMemory localDirectory, template="<L2Cache_DirEntry>"; void set_cache_entry(AbstractCacheEntry b); diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm index 0dd4239a9..f458fccd8 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm @@ -1,4 +1,3 @@ - /* * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood * All rights reserved. @@ -119,7 +118,7 @@ machine(Directory, "Directory protocol") } // ** OBJECTS ** - TBETable TBEs, template="<Directory_TBE>"; + TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs"; void set_tbe(TBE b); void unset_tbe(); diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm index e0a8a3eb5..6d10305ea 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -44,7 +44,7 @@ machine(DMA, "DMA Controller") MessageBuffer mandatoryQueue, ordered="false"; MessageBuffer triggerQueue, ordered="true"; - TBETable TBEs, template="<DMA_TBE>"; + TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs"; State cur_state; void set_tbe(TBE b); diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm index 8cf40974e..a5de5e832 100644 --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm @@ -180,7 +180,7 @@ machine(L1Cache, "Token protocol") void wakeUpAllBuffers(); void wakeUpBuffers(Address a); - TBETable L1_TBEs, template="<L1Cache_TBE>"; + TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true"; diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm index fd51e2924..5a604555e 100644 --- a/src/mem/protocol/MOESI_CMP_token-dir.sm +++ b/src/mem/protocol/MOESI_CMP_token-dir.sm @@ -157,7 +157,7 @@ machine(Directory, "Token protocol") PersistentTable persistentTable; TimerTable reissueTimerTable; - TBETable TBEs, template="<Directory_TBE>"; + TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs"; bool starving, default="false"; int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm index a3fa1219f..0f35b4277 100644 --- a/src/mem/protocol/MOESI_hammer-cache.sm +++ b/src/mem/protocol/MOESI_hammer-cache.sm @@ -173,7 +173,7 @@ machine(L1Cache, "AMD Hammer-like protocol") bool isPresent(Address); } - TBETable TBEs, template="<L1Cache_TBE>"; + TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; void set_cache_entry(AbstractCacheEntry b); void unset_cache_entry(); diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm index 22ca568a8..5b752f781 100644 --- a/src/mem/protocol/MOESI_hammer-dir.sm +++ b/src/mem/protocol/MOESI_hammer-dir.sm @@ -184,7 +184,7 @@ machine(Directory, "AMD Hammer-like protocol") Set fwd_set; - TBETable TBEs, template="<Directory_TBE>"; + TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs"; Entry getDirectoryEntry(Address addr), return_by_pointer="yes" { Entry dir_entry := static_cast(Entry, "pointer", directory[addr]); diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm index 64b156938..1e49e1d7b 100644 --- a/src/mem/protocol/Network_test-cache.sm +++ b/src/mem/protocol/Network_test-cache.sm @@ -66,25 +66,6 @@ machine(L1Cache, "Network_test L1 Cache") DataBlock DataBlk, desc="Data in the block"; } - // TBE fields - structure(TBE, desc="...") { - State TBEState, desc="Transient state"; - DataBlock DataBlk, desc="data for the block, required for concurrent writebacks"; - } - - structure(TBETable, external="yes") { - TBE lookup(Address); - void allocate(Address); - void deallocate(Address); - bool isPresent(Address); - } - - - // STRUCTURES - - TBETable TBEs, template="<L1Cache_TBE>"; - - // FUNCTIONS // cpu/testers/networktest/networktest.cc generates packets of the type @@ -112,11 +93,11 @@ machine(L1Cache, "Network_test L1 Cache") } - State getState(TBE tbe, Entry cache_entry, Address addr) { + State getState(Entry cache_entry, Address addr) { return State:I; } - void setState(TBE tbe, Entry cache_entry, Address addr, State state) { + void setState(Entry cache_entry, Address addr, State state) { } @@ -146,9 +127,7 @@ machine(L1Cache, "Network_test L1 Cache") if (mandatoryQueue_in.isReady()) { peek(mandatoryQueue_in, RubyRequest) { trigger(mandatory_request_type_to_event(in_msg.Type), - in_msg.LineAddress, - getCacheEntry(in_msg.LineAddress), - TBEs[in_msg.LineAddress]); + in_msg.LineAddress, getCacheEntry(in_msg.LineAddress)); } } } diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm index 2a4281757..6c8cfc832 100644 --- a/src/mem/protocol/RubySlicc_Exports.sm +++ b/src/mem/protocol/RubySlicc_Exports.sm @@ -31,6 +31,7 @@ external_type(int, primitive="yes", default="0"); external_type(bool, primitive="yes", default="false"); external_type(std::string, primitive="yes"); +external_type(uint32_t, primitive="yes"); external_type(uint64, primitive="yes"); external_type(Time, primitive="yes", default="0"); external_type(PacketPtr, primitive="yes"); |