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-rw-r--r--src/mem/protocol/MESI_CMP_directory-L1cache.sm13
-rw-r--r--src/mem/protocol/RubySlicc_Types.sm1
2 files changed, 13 insertions, 1 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
index 113421842..f8d731ee1 100644
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
@@ -782,6 +782,11 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
}
}
+ action(dg_invalidate_sc, "dg",
+ desc="Invalidate store conditional as the cache lost permissions") {
+ sequencer.invalidateSC(address);
+ }
+
action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load completed.") {
assert(is_valid(cache_entry));
DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk);
@@ -1251,7 +1256,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
}
// Transitions from IM
- transition({IM, SM}, Inv, IM) {
+ transition(IM, Inv, IM) {
fi_sendInvAck;
l_popRequestQueue;
}
@@ -1292,6 +1297,12 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
}
// transitions from SM
+ transition(SM, Inv, IM) {
+ fi_sendInvAck;
+ dg_invalidate_sc;
+ l_popRequestQueue;
+ }
+
transition({SM, IM, PF_SM, PF_IM}, Ack) {
q_updateAckCount;
o_popIncomingResponseQueue;
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index 096215386..c94020792 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -110,6 +110,7 @@ structure (Sequencer, external = "yes") {
void evictionCallback(Address);
void recordRequestType(SequencerRequestType);
bool checkResourceAvailable(CacheResourceType, Address);
+ void invalidateSC(Address);
}
structure(RubyRequest, desc="...", interface="Message", external="yes") {