diff options
Diffstat (limited to 'src/mem/ruby/config/MI_example-homogeneous.rb')
| -rw-r--r-- | src/mem/ruby/config/MI_example-homogeneous.rb | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/mem/ruby/config/MI_example-homogeneous.rb b/src/mem/ruby/config/MI_example-homogeneous.rb index 451281f20..2b416e647 100644 --- a/src/mem/ruby/config/MI_example-homogeneous.rb +++ b/src/mem/ruby/config/MI_example-homogeneous.rb @@ -8,15 +8,17 @@ require "cfg.rb" +RubySystem.reset + # default values num_cores = 2 -L1_CACHE_SIZE_KB = 32 -L1_CACHE_ASSOC = 8 -L1_CACHE_LATENCY = 1 +l1_cache_size_kb = 32 +l1_cache_assoc = 8 +l1_cache_latency = 1 num_memories = 2 memory_size_mb = 1024 -NUM_DMA = 1 +num_dma = 1 protocol = "MI_example" # check for overrides @@ -46,7 +48,7 @@ assert(protocol == "MI_example", __FILE__ + " cannot be used with protocol " + p require protocol+".rb" num_cores.times { |n| - cache = SetAssociativeCache.new("l1u_"+n.to_s, L1_CACHE_SIZE_KB, L1_CACHE_LATENCY, L1_CACHE_ASSOC, "PSEUDO_LRU") + cache = SetAssociativeCache.new("l1u_"+n.to_s, l1_cache_size_kb, l1_cache_latency, l1_cache_assoc, "PSEUDO_LRU") sequencer = Sequencer.new("Sequencer_"+n.to_s, cache, cache) iface_ports << sequencer net_ports << MI_example_CacheController.new("L1CacheController_"+n.to_s, @@ -61,7 +63,7 @@ num_memories.times { |n| "Directory", directory, memory_control) } -NUM_DMA.times { |n| +num_dma.times { |n| dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s) iface_ports << dma_sequencer net_ports << MI_example_DMAController.new("DMAController_"+n.to_s, "DMA", dma_sequencer) |