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-rw-r--r--src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb36
1 files changed, 34 insertions, 2 deletions
diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
index 8a202d450..83020742e 100644
--- a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
+++ b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb
@@ -26,7 +26,7 @@ num_memories = 1
memory_size_mb = 1024
num_dma = 1
-protocol = "MOESI_CMP_directory"
+protocol = "MESI_CMP_directory"
# check for overrides
@@ -49,7 +49,7 @@ end
net_ports = Array.new
iface_ports = Array.new
-assert(protocol == "MOESI_CMP_directory", __FILE__+" cannot be used with protocol "+protocol);
+#assert(protocol == "MESI_CMP_directory", __FILE__+" cannot be used with protocol "+protocol);
require protocol+".rb"
@@ -65,6 +65,14 @@ num_cores.times { |n|
sequencer,
num_l2_banks)
end
+
+ if protocol == "MESI_CMP_directory"
+ net_ports << MESI_CMP_directory_L1CacheController.new("L1CacheController_"+n.to_s,
+ "L1Cache",
+ icache, dcache,
+ sequencer,
+ num_l2_banks)
+ end
}
num_l2_banks.times { |n|
cache = SetAssociativeCache.new("l2u_"+n.to_s, l2_cache_size_kb/num_l2_banks, l2_cache_latency, l2_cache_assoc, "PSEUDO_LRU")
@@ -73,6 +81,14 @@ num_l2_banks.times { |n|
"L2Cache",
cache)
end
+
+ if protocol == "MESI_CMP_directory"
+ net_ports << MESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s,
+ "L2Cache",
+ cache)
+ end
+
+
}
num_memories.times { |n|
directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s, memory_size_mb/num_memories)
@@ -83,6 +99,14 @@ num_memories.times { |n|
directory,
memory_control)
end
+
+ if protocol == "MESI_CMP_directory"
+ net_ports << MESI_CMP_directory_DirectoryController.new("DirectoryController_"+n.to_s,
+ "Directory",
+ directory,
+ memory_control)
+ end
+
}
num_dma.times { |n|
dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s)
@@ -92,6 +116,14 @@ num_dma.times { |n|
"DMA",
dma_sequencer)
end
+
+ if protocol == "MESI_CMP_directory"
+ net_ports << MESI_CMP_directory_DMAController.new("DMAController_"+n.to_s,
+ "DMA",
+ dma_sequencer)
+ end
+
+
}
topology = CrossbarTopology.new("theTopology", net_ports)