diff options
Diffstat (limited to 'src/mem/ruby/config')
| -rw-r--r-- | src/mem/ruby/config/MESI_CMP_directory.rb | 75 | ||||
| -rw-r--r-- | src/mem/ruby/config/MI_example-homogeneous.rb | 91 | ||||
| -rw-r--r-- | src/mem/ruby/config/MI_example.rb | 37 | ||||
| -rw-r--r-- | src/mem/ruby/config/MOESI_CMP_directory.rb | 69 | ||||
| -rw-r--r-- | src/mem/ruby/config/MOESI_CMP_token.rb | 92 | ||||
| -rw-r--r-- | src/mem/ruby/config/MOESI_hammer-homogeneous.rb | 109 | ||||
| -rw-r--r-- | src/mem/ruby/config/MOESI_hammer.rb | 41 | ||||
| -rw-r--r-- | src/mem/ruby/config/SConscript | 35 | ||||
| -rw-r--r-- | src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb | 139 | ||||
| -rw-r--r-- | src/mem/ruby/config/assert.rb | 18 | ||||
| -rw-r--r-- | src/mem/ruby/config/cfg.rb | 672 | ||||
| -rw-r--r-- | src/mem/ruby/config/defaults.rb | 248 | ||||
| -rw-r--r-- | src/mem/ruby/config/libruby_cfg_test.cc | 14 | ||||
| -rw-r--r-- | src/mem/ruby/config/print_cfg.rb | 14 | ||||
| -rw-r--r-- | src/mem/ruby/config/util.rb | 10 |
15 files changed, 0 insertions, 1664 deletions
diff --git a/src/mem/ruby/config/MESI_CMP_directory.rb b/src/mem/ruby/config/MESI_CMP_directory.rb deleted file mode 100644 index 7a9d47f24..000000000 --- a/src/mem/ruby/config/MESI_CMP_directory.rb +++ /dev/null @@ -1,75 +0,0 @@ -require "cfg.rb" -require "util.rb" - - -class MESI_CMP_directory_L2CacheController < CacheController - attr :cache - - def initialize(obj_name, mach_type, cache) - super(obj_name, mach_type, [cache]) - @cache = cache - end - def argv() - vec = super() - vec += " cache " + cache.obj_name - vec += " l2_request_latency "+request_latency.to_s - vec += " l2_response_latency "+response_latency.to_s - vec += " to_l1_latency "+to_L1_latency.to_s - return vec - end - -end - -class MESI_CMP_directory_L1CacheController < L1CacheController - attr :icache, :dcache - attr :num_l2_controllers - - def initialize(obj_name, mach_type, icache, dcache, sequencer, num_l2_controllers) - super(obj_name, mach_type, [icache, dcache], sequencer) - @icache = icache - @dcache = dcache - @num_l2_controllers = num_l2_controllers - end - - def argv() - num_select_bits = log_int(num_l2_controllers) - num_block_bits = log_int(RubySystem.block_size_bytes) - l2_select_low_bit = num_block_bits - - vec = super() - vec += " icache " + @icache.obj_name - vec += " dcache " + @dcache.obj_name - vec += " l1_request_latency "+l1_request_latency.to_s - vec += " l1_response_latency "+l1_response_latency.to_s - vec += " to_l2_latency "+to_L2_latency.to_s - vec += " l2_select_low_bit " + l2_select_low_bit.to_s - vec += " l2_select_num_bits " + num_select_bits.to_s - return vec - end - -end - -class MESI_CMP_directory_DMAController < DMAController - def initialize(obj_name, mach_type, dma_sequencer) - super(obj_name, mach_type, dma_sequencer) - end - def argv() - vec = super - vec += " request_latency "+request_latency.to_s - return vec - end -end - - -class MESI_CMP_directory_DirectoryController < DirectoryController - def initialize(obj_name, mach_type, directory, memory_control) - super(obj_name, mach_type, directory, memory_control) - end - def argv() - vec = super() - vec += " to_mem_ctrl_latency "+to_mem_ctrl_latency.to_s - vec += " directory_latency "+directory_latency.to_s - end - -end -require "defaults.rb" diff --git a/src/mem/ruby/config/MI_example-homogeneous.rb b/src/mem/ruby/config/MI_example-homogeneous.rb deleted file mode 100644 index d409e6782..000000000 --- a/src/mem/ruby/config/MI_example-homogeneous.rb +++ /dev/null @@ -1,91 +0,0 @@ -#!/usr/bin/ruby -# -# Creates a homogeneous CMP system with a single unified cache per -# core and a crossbar network. Uses the default parameters listed -# below, which can be overridden if a wrapper script sets the hash -# libruby_args. -# - -require "cfg.rb" - -RubySystem.reset - -# default values - -num_cores = 2 -l1_cache_size_bytes = 32768 -l1_cache_assoc = 8 -l1_cache_latency = 1 -num_memories = 2 -memory_size_mb = 1024 -num_dma = 1 -protocol = "MI_example" - -# check for overrides - - -for i in 0..$*.size-1 do - if $*[i] == "-c" - protocol = $*[i+1] - i = i+1 - elsif $*[i] == "-p" - num_cores = $*[i+1].to_i - i = i+1 - elsif $*[i] == "-m" - num_memories = $*[i+1].to_i - i = i+1 - elsif $*[i] == "-R" - if $*[i+1] == "rand" - RubySystem.random_seed = "rand" - else - RubySystem.random_seed = $*[i+1].to_i - end - i = i+ 1 - elsif $*[i] == "-s" - memory_size_mb = $*[i+1].to_i - i = i + 1 - elsif $*[i] == "-C" - l1_cache_size_bytes = $*[i+1].to_i - i = i + 1 - elsif $*[i] == "-A" - l1_cache_assoc = $*[i+1].to_i - i = i + 1 - elsif $*[i] == "-D" - num_dma = $*[i+1].to_i - i = i + 1 - end -end - -net_ports = Array.new -iface_ports = Array.new - -assert(protocol == "MI_example", __FILE__ + " cannot be used with protocol " + protocol) - -require protocol+".rb" - -num_cores.times { |n| - cache = SetAssociativeCache.new("l1u_"+n.to_s, l1_cache_size_bytes, l1_cache_latency, l1_cache_assoc, "PSEUDO_LRU") - sequencer = Sequencer.new("Sequencer_"+n.to_s, cache, cache) - iface_ports << sequencer - net_ports << MI_example_CacheController.new("L1CacheController_"+n.to_s, - "L1Cache", - cache, - sequencer) -} -num_memories.times { |n| - directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s, memory_size_mb/num_memories) - memory_control = MemoryControl.new("MemoryControl_"+n.to_s) - net_ports << MI_example_DirectoryController.new("DirectoryController_"+n.to_s, - "Directory", - directory, memory_control) -} -num_dma.times { |n| - dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s) - iface_ports << dma_sequencer - net_ports << MI_example_DMAController.new("DMAController_"+n.to_s, "DMA", dma_sequencer) -} - -topology = CrossbarTopology.new("theTopology", net_ports) -on_chip_net = Network.new("theNetwork", topology) - -RubySystem.init(iface_ports, on_chip_net) diff --git a/src/mem/ruby/config/MI_example.rb b/src/mem/ruby/config/MI_example.rb deleted file mode 100644 index 8113087aa..000000000 --- a/src/mem/ruby/config/MI_example.rb +++ /dev/null @@ -1,37 +0,0 @@ - -require "util.rb" - -class MI_example_CacheController < L1CacheController - attr :cache - def initialize(obj_name, mach_type, cache, sequencer) - super(obj_name, mach_type, [cache], sequencer) - @cache = cache - end - def argv() - vec = super() - vec += " cache " + @cache.obj_name - vec += " issue_latency "+issue_latency.to_s - vec += " cache_response_latency "+cache_response_latency.to_s - end - -end - -class MI_example_DirectoryController < DirectoryController - def initialize(obj_name, mach_type, directory, memory_control) - super(obj_name, mach_type, directory, memory_control) - end - def argv() - vec = super() - vec += " directory_latency "+directory_latency.to_s - end -end - -class MI_example_DMAController < DMAController - def initialize(obj_name, mach_type, dma_sequencer) - super(obj_name, mach_type, dma_sequencer) - end - def argv() - vec = super - vec += " request_latency "+request_latency.to_s - end -end diff --git a/src/mem/ruby/config/MOESI_CMP_directory.rb b/src/mem/ruby/config/MOESI_CMP_directory.rb deleted file mode 100644 index 1e8a82fab..000000000 --- a/src/mem/ruby/config/MOESI_CMP_directory.rb +++ /dev/null @@ -1,69 +0,0 @@ - -require "cfg.rb" -require "util.rb" - - -class MOESI_CMP_directory_L1CacheController < L1CacheController - attr :icache, :dcache - attr :num_l2_controllers - def initialize(obj_name, mach_type, icache, dcache, sequencer, num_l2_controllers) - super(obj_name, mach_type, [icache, dcache], sequencer) - @icache = icache - @dcache = dcache - @num_l2_controllers = num_l2_controllers - end - def argv() - num_select_bits = log_int(num_l2_controllers) - num_block_bits = log_int(RubySystem.block_size_bytes) - - l2_select_low_bit = num_block_bits - - vec = super() - vec += " icache " + @icache.obj_name - vec += " dcache " + @dcache.obj_name - vec += " request_latency "+request_latency().to_s - vec += " l2_select_low_bit " + l2_select_low_bit.to_s - vec += " l2_select_num_bits " + num_select_bits.to_s - return vec - end -end - -class MOESI_CMP_directory_L2CacheController < CacheController - attr :cache - def initialize(obj_name, mach_type, cache) - super(obj_name, mach_type, [cache]) - @cache = cache - end - def argv() - vec = super() - vec += " cache " + @cache.obj_name - vec += " request_latency "+request_latency().to_s - vec += " response_latency "+response_latency().to_s - return vec - end -end - - -class MOESI_CMP_directory_DirectoryController < DirectoryController - def initialize(obj_name, mach_type, directory, memory_control) - super(obj_name, mach_type, directory, memory_control) - end - def argv() - vec = super() - vec += " directory_latency "+directory_latency.to_s - return vec - end - -end - -class MOESI_CMP_directory_DMAController < DMAController - def initialize(obj_name, mach_type, dma_sequencer) - super(obj_name, mach_type, dma_sequencer) - end - def argv() - vec = super - vec += " request_latency "+request_latency.to_s - vec += " response_latency "+response_latency.to_s - return vec - end -end diff --git a/src/mem/ruby/config/MOESI_CMP_token.rb b/src/mem/ruby/config/MOESI_CMP_token.rb deleted file mode 100644 index ba963dc06..000000000 --- a/src/mem/ruby/config/MOESI_CMP_token.rb +++ /dev/null @@ -1,92 +0,0 @@ - -require "cfg.rb" -require "util.rb" - - -class MOESI_CMP_token_L1CacheController < L1CacheController - attr :icache, :dcache - attr :num_l2_controllers - attr :n_tokens - def initialize(obj_name, mach_type, icache, dcache, sequencer, num_l2_controllers, n_tokens) - super(obj_name, mach_type, [icache, dcache], sequencer) - @icache = icache - @dcache = dcache - @num_l2_controllers = num_l2_controllers - @n_tokens = n_tokens - end - def argv() - num_select_bits = log_int(num_l2_controllers) - num_block_bits = log_int(RubySystem.block_size_bytes) - - l2_select_low_bit = num_block_bits - - vec = super() - vec += " icache " + @icache.obj_name - vec += " dcache " + @dcache.obj_name - vec += " l1_request_latency " + l1_request_latency.to_s - vec += " l1_response_latency " + l1_response_latency.to_s - vec += " l2_select_low_bit " + l2_select_low_bit.to_s - vec += " l2_select_num_bits " + num_select_bits.to_s - vec += " N_tokens " + n_tokens.to_s - vec += " retry_threshold " + retry_threshold.to_s - vec += " fixed_timeout_latency " + fixed_timeout_latency.to_s - vec += " dynamic_timeout_enabled " + dynamic_timeout_enabled.to_s - - return vec - end -end - -class MOESI_CMP_token_L2CacheController < CacheController - attr :cache - attr :n_tokens - def initialize(obj_name, mach_type, cache, n_tokens) - super(obj_name, mach_type, [cache]) - @cache = cache - @n_tokens = n_tokens - end - def argv() - vec = super() - vec += " cache " + @cache.obj_name - vec += " l2_request_latency " + l2_request_latency.to_s - vec += " l2_response_latency " + l2_response_latency.to_s - vec += " N_tokens " + n_tokens.to_s - vec += " filtering_enabled " + filtering_enabled.to_s - return vec - end -end - - -class MOESI_CMP_token_DirectoryController < DirectoryController - attr :num_l2_controllers - def initialize(obj_name, mach_type, directory, memory_control, num_l2_controllers) - super(obj_name, mach_type, directory, memory_control) - @num_l2_controllers = num_l2_controllers - end - def argv() - num_select_bits = log_int(num_l2_controllers) - num_block_bits = log_int(RubySystem.block_size_bytes) - - l2_select_low_bit = num_block_bits - - vec = super() - vec += " directory_latency "+directory_latency.to_s - vec += " l2_select_low_bit " + l2_select_low_bit.to_s - vec += " l2_select_num_bits " + num_select_bits.to_s - vec += " distributed_persistent "+distributed_persistent.to_s - vec += " fixed_timeout_latency " + fixed_timeout_latency.to_s - return vec - end - -end - -class MOESI_CMP_token_DMAController < DMAController - def initialize(obj_name, mach_type, dma_sequencer) - super(obj_name, mach_type, dma_sequencer) - end - def argv() - vec = super - vec += " request_latency "+request_latency.to_s - vec += " response_latency "+response_latency.to_s - return vec - end -end diff --git a/src/mem/ruby/config/MOESI_hammer-homogeneous.rb b/src/mem/ruby/config/MOESI_hammer-homogeneous.rb deleted file mode 100644 index 02af0ec27..000000000 --- a/src/mem/ruby/config/MOESI_hammer-homogeneous.rb +++ /dev/null @@ -1,109 +0,0 @@ -#!/usr/bin/ruby -# -# Creates multiple on-chip nodes with three level of cache. -# - -require "cfg.rb" - -RubySystem.reset - -# default values - -num_cores = 2 -l1_cache_size_bytes = 32768 -l1_cache_assoc = 2 -l1_cache_latency = 3 -l2_cache_size_bytes = 1048576 -l2_cache_assoc = 16 -l2_cache_latency = 15 -num_memories = 2 -memory_size_mb = 1024 -num_dma = 0 -use_map = false -map_levels = 4 -protocol = "MOESI_hammer" - -# check for overrides - - -for i in 0..$*.size-1 do - if $*[i] == "-c" - protocol = $*[i+1] - i = i+1 - elsif $*[i] == "-p" - num_cores = $*[i+1].to_i - i = i+1 - elsif $*[i] == "-m" - num_memories = $*[i+1].to_i - i = i+1 - elsif $*[i] == "-s" - memory_size_mb = $*[i+1].to_i - i = i + 1 - elsif $*[i] == "-U" - use_map = $*[i+1] - i = i + 1 - elsif $*[i] == "-C" - l1_cache_size_bytes = $*[i+1].to_i - i = i + 1 - elsif $*[i] == "-A" - l1_cache_assoc = $*[i+1].to_i - i = i + 1 - elsif $*[i] == "-M" - map_levels = $*[i+1].to_i - i = i + 1 - elsif $*[i] == "-D" - num_dma = $*[i+1].to_i - i = i + 1 - end -end - -net_ports = Array.new -iface_ports = Array.new - -assert(protocol == "MOESI_hammer", __FILE__ + " cannot be used with protocol " + protocol) - -require protocol+".rb" - -num_cores.times { |n| - icache = SetAssociativeCache.new("l1i_"+n.to_s, - l1_cache_size_bytes, - l1_cache_latency, - l1_cache_assoc, - "PSEUDO_LRU") - dcache = SetAssociativeCache.new("l1d_"+n.to_s, - l1_cache_size_bytes, - l1_cache_latency, - l1_cache_assoc, - "PSEUDO_LRU") - l2cache = SetAssociativeCache.new("l2u_"+n.to_s, - l2_cache_size_bytes, - l2_cache_latency, - l2_cache_assoc, - "PSEUDO_LRU") - sequencer = Sequencer.new("Sequencer_"+n.to_s, icache, dcache) - iface_ports << sequencer - net_ports << MOESI_hammer_CacheController.new("L1CacheController_"+n.to_s, - "L1Cache", - icache, - dcache, - l2cache, - sequencer) -} -num_memories.times { |n| - directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s, memory_size_mb/num_memories) - memory_control = MemoryControl.new("MemoryControl_"+n.to_s) - net_ports << MOESI_hammer_DirectoryController.new("DirectoryController_"+n.to_s, - "Directory", - directory, - memory_control) -} -num_dma.times { |n| - dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s) - iface_ports << dma_sequencer - net_ports << MOESI_hammer_DMAController.new("DMAController_"+n.to_s, "DMA", dma_sequencer) -} - -topology = CrossbarTopology.new("theTopology", net_ports) -on_chip_net = Network.new("theNetwork", topology) - -RubySystem.init(iface_ports, on_chip_net) diff --git a/src/mem/ruby/config/MOESI_hammer.rb b/src/mem/ruby/config/MOESI_hammer.rb deleted file mode 100644 index d3735028b..000000000 --- a/src/mem/ruby/config/MOESI_hammer.rb +++ /dev/null @@ -1,41 +0,0 @@ - -require "util.rb" - -class MOESI_hammer_CacheController < L1CacheController - attr :cache - def initialize(obj_name, mach_type, icache, dcache, l2cache, sequencer) - super(obj_name, mach_type, [icache, dcache, l2cache], sequencer) - @icache = icache - @dcache = dcache - @l2cache = l2cache - end - def argv() - vec = super() - vec += " icache " + @icache.obj_name - vec += " dcache " + @dcache.obj_name - vec += " l2cache " + @l2cache.obj_name - vec += " issue_latency "+issue_latency.to_s - vec += " cache_response_latency "+cache_response_latency.to_s - end - -end - -class MOESI_hammer_DirectoryController < DirectoryController - def initialize(obj_name, mach_type, directory, memory_control) - super(obj_name, mach_type, directory, memory_control) - end - def argv() - vec = super() - vec += " memory_controller_latency "+memory_controller_latency.to_s - end -end - -class MOESI_hammer_DMAController < DMAController - def initialize(obj_name, mach_type, dma_sequencer) - super(obj_name, mach_type, dma_sequencer) - end - def argv() - vec = super - vec += " request_latency "+request_latency.to_s - end -end diff --git a/src/mem/ruby/config/SConscript b/src/mem/ruby/config/SConscript deleted file mode 100644 index bf8352576..000000000 --- a/src/mem/ruby/config/SConscript +++ /dev/null @@ -1,35 +0,0 @@ -# -*- mode:python -*- - -# Copyright (c) 2009 The Hewlett-Packard Development Company -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Nathan Binkert - -Import('*') - -if not env['RUBY']: - Return() - diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb deleted file mode 100644 index ee22df656..000000000 --- a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb +++ /dev/null @@ -1,139 +0,0 @@ -#!/usr/bin/ruby -# -# Creates a homogeneous CMP system with a single unified cache per -# core and a crossbar network. Uses the default parameters listed -# below, which can be overridden using command line args. -# - -require "cfg.rb" - -RubySystem.reset - -# default values - -num_cores = 2 -l1_icache_size_kb = 64 -l1_icache_assoc = 8 -l1_icache_latency = 1 -l1_dcache_size_kb = 32 -l1_dcache_assoc = 8 -l1_dcache_latency = 1 -l2_cache_size_kb = 8192 # total size (sum of all banks) -l2_cache_assoc = 16 -l2_cache_latency = 12 -num_l2_banks = num_cores -num_memories = 1 -memory_size_mb = 1024 -num_dma = 1 - -#default protocol -protocol = "MOESI_CMP_directory" - -# check for overrides - -for i in 0..$*.size-1 do - if $*[i] == "-c" or $*[i] == "--protocol" - i += 1 - protocol = $*[i] - elsif $*[i] == "-A" - l1_dcache_size_kb = $*[i+1].to_i - i = i+1 - elsif $*[i] == "-B" - num_l2_banks = $*[i+1].to_i - i = i+1 - elsif $*[i] == "-m" - num_memories = $*[i+1].to_i - i = i+1 - elsif $*[i] == "-p" - num_cores = $*[i+1].to_i - i = i+1 - elsif $*[i] == "-R" - if $*[i+1] == "rand" - RubySystem.random_seed = "rand" - else - RubySystem.random_seed = $*[i+1].to_i - end - i = i+ 1 - elsif $*[i] == "-s" - memory_size_mb = $*[i+1].to_i - i = i + 1 - end -end - -net_ports = Array.new -iface_ports = Array.new - -assert((protocol == "MESI_CMP_directory" or protocol == "MOESI_CMP_directory"), __FILE__+" cannot be used with protocol '#{protocol}'"); - -require protocol+".rb" - -num_cores.times { |n| - icache = SetAssociativeCache.new("l1i_"+n.to_s, l1_icache_size_kb*1024, l1_icache_latency, l1_icache_assoc, "PSEUDO_LRU") - dcache = SetAssociativeCache.new("l1d_"+n.to_s, l1_dcache_size_kb*1024, l1_dcache_latency, l1_dcache_assoc, "PSEUDO_LRU") - sequencer = Sequencer.new("Sequencer_"+n.to_s, icache, dcache) - iface_ports << sequencer - if protocol == "MOESI_CMP_directory" - net_ports << MOESI_CMP_directory_L1CacheController.new("L1CacheController_"+n.to_s, - "L1Cache", - icache, dcache, - sequencer, - num_l2_banks) - elsif protocol == "MESI_CMP_directory" - net_ports << MESI_CMP_directory_L1CacheController.new("L1CacheController_"+n.to_s, - "L1Cache", - icache, dcache, - sequencer, - num_l2_banks) - end -} -num_l2_banks.times { |n| - cache = SetAssociativeCache.new("l2u_"+n.to_s, (l2_cache_size_kb*1024)/num_l2_banks, l2_cache_latency, l2_cache_assoc, "PSEUDO_LRU") - if protocol == "MOESI_CMP_directory" - net_ports << MOESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s, - "L2Cache", - cache) - elsif protocol == "MESI_CMP_directory" - net_ports << MESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s, - "L2Cache", - cache) - end - - net_ports.last.request_latency = l2_cache_latency + 2 - net_ports.last.response_latency = l2_cache_latency + 2 -} -num_memories.times { |n| - directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s, memory_size_mb/num_memories) - memory_control = MemoryControl.new("MemoryControl_"+n.to_s) - if protocol == "MOESI_CMP_directory" - net_ports << MOESI_CMP_directory_DirectoryController.new("DirectoryController_"+n.to_s, - "Directory", - directory, - memory_control) - elsif protocol == "MESI_CMP_directory" - net_ports << MESI_CMP_directory_DirectoryController.new("DirectoryController_"+n.to_s, - "Directory", - directory, - memory_control) - end - -} -num_dma.times { |n| - dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s) - iface_ports << dma_sequencer - if protocol == "MOESI_CMP_directory" - net_ports << MOESI_CMP_directory_DMAController.new("DMAController_"+n.to_s, - "DMA", - dma_sequencer) - elsif protocol == "MESI_CMP_directory" - net_ports << MESI_CMP_directory_DMAController.new("DMAController_"+n.to_s, - "DMA", - dma_sequencer) - end - - -} - -topology = CrossbarTopology.new("theTopology", net_ports) -on_chip_net = Network.new("theNetwork", topology) - -RubySystem.init(iface_ports, on_chip_net) diff --git a/src/mem/ruby/config/assert.rb b/src/mem/ruby/config/assert.rb deleted file mode 100644 index cc3e43214..000000000 --- a/src/mem/ruby/config/assert.rb +++ /dev/null @@ -1,18 +0,0 @@ -#!/usr/bin/env ruby - -class AssertionFailure < RuntimeError - attr_reader :msg, :output - def initialize(message, out=nil) - @msg = message - @output = out - end -end - -class NotImplementedException < Exception -end - -def assert(condition,message) - unless condition - raise AssertionFailure.new(message), "\n\nAssertion failed: \n\n #{message}\n\n" - end -end diff --git a/src/mem/ruby/config/cfg.rb b/src/mem/ruby/config/cfg.rb deleted file mode 100644 index a20562243..000000000 --- a/src/mem/ruby/config/cfg.rb +++ /dev/null @@ -1,672 +0,0 @@ -#!/usr/bin/ruby - -root = File.dirname(File.expand_path(__FILE__)) -require root+'/assert.rb' - -class Boolean - def self.is_a?(obj) - return self.name == "Boolean" - end -end - -class LibRubyObject - @@all_objs = Array.new - @@default_params = Hash.new - @@param_types = Hash.new - - attr_reader :obj_name - - def initialize(obj_name) - assert obj_name.is_a?(String), "Obj_Name must be a string" - @obj_name = obj_name - @@all_objs << self - @params = Hash.new - - # add all parent parameter accessors if they don't exist - self.class.ancestors.each { |ancestor| - if @@default_params.key?(ancestor.name.to_sym) - @@default_params[ancestor.name.to_sym].each { |p, default| - p = p.to_sym - @params[p] = default - if ! respond_to?(p) - self.class.send(:define_method, p) { - @params[p] = @@default_params[ancestor.name.to_sym][p] if ! @params.key?(p) - return @params[p] - } - end - setter_method_name = (p.to_s + "=").to_sym - if ! respond_to?(setter_method_name) - self.class.send(:define_method, setter_method_name) { |val| - type = @@param_types[ancestor.name.to_sym][p] - if val.is_a?(FalseClass) || val.is_a?(TrueClass) - assert type.is_a?(Boolean), "default value of param \"#{p}\" must be either true or false" - else - assert val.is_a?(type), "default value of param \"#{p}\", which is of type #{val.class.name} does not match expected type #{type}" - end - @params[p] = val - } - end - } - end - } - end - - def cppClassName() - raise NotImplementedException - end - - def self.param(param_name, type) - idx = self.name.to_sym - @@default_params[idx] = Hash.new if ! @@default_params.key?(idx) - @@default_params[idx][param_name] = nil - @@param_types[idx] = Hash.new if ! @@param_types.key?(idx) - @@param_types[idx][param_name] = type - end - - def self.default_param(param_name, type, default) - - if default.is_a?(FalseClass) || default.is_a?(TrueClass) - assert type.is_a?(Boolean), "default value of param \"#{param_name}\" must be either true or false" - else - assert default.is_a?(type), "default value of param \"#{param_name}\" does not match type #{type}" - end - - idx = self.name.to_sym - @@default_params[idx] = Hash.new if ! @@default_params.key?(idx) - @@default_params[idx][param_name] = default - @@param_types[idx] = Hash.new if ! @@param_types.key?(idx) - @@param_types[idx][param_name] = type - - end - - def applyDefaults() - idx = self.class.name.to_sym - @@default_params[idx] = Hash.new if ! @@default_params.key?(idx) - @@default_params[idx].each { |key, val| - @params[key] = val if ! @params.key?(key) - } - end - - def argv() - str = "" - - applyDefaults - - @params.each { |key, val| - str += key.id2name + " " - assert(val != nil, "parameter #{key} is nil") - if val.is_a?(LibRubyObject) - str += val.obj_name + " " - else - if val.is_a?(String) and val == "" - str += "null " - else - str += val.to_s + " " - end - end - } - return str - end - - def self.printConstructors() - str = "" - @@all_objs.each { |obj| - str += obj.cppClassName + " " + obj.obj_name + " " + obj.argv + "\n" - } - return str - end - def self.all() - @@all_objs - end -end - -class IfacePort < LibRubyObject - def initialize(obj_name) - super(obj_name) - end - - def bochsConnType - raise NotImplementedException - end -end - -class NetPort < LibRubyObject - attr :mach_type - param :version, Integer - - @@type_cnt = Hash.new - def initialize(obj_name, mach_type) - super(obj_name) - @mach_type = mach_type - @@type_cnt[mach_type] ||= 0 - self.version= @@type_cnt[mach_type] # sets the version parameter - - @@type_cnt[mach_type] += 1 - - end - - def port_name - mach_type - end - def port_num - version - end - def self.totalOfType(mach_type) - return @@type_cnt[mach_type] - end - def cppClassName() - "generated:"+@mach_type - end - -end - -class MemoryVector < LibRubyObject - def initialize(obj_name) - super(obj_name) - end - - def cppClassName - "MemoryVector" - end -end - -class Debug < LibRubyObject - def initialize *args - case args.size - when 1 - super(args[0]) - when 6 - init_params *args[1] - else - raise Exception - end - end - - def init_params (protocol_trace, filter_string, verbosity_string, start_time, output_filename) - @params[:protocol_trace] = protocol_trace - @params[:filter_string] = filter_string - @params[:verbosity_string] = verbosity_string - @params[:start_time] = start_time - @params[:output_filename] = output_filename - end - - def cppClassName - "Debug" - end -end - -class RubySystem - - @@params = Hash.new - @@defaults = Hash.new - @@network = nil - - def self.init(iface_ports, network) - @@iface_ports = iface_ports - @@network = network - end - - def self.reset() - @@iface_ports = nil - @@network = nil - @@params.each { |param_name, param| - param = @@defaults[param_name] - } - end - - def self.default_param(param_name, type, default) - if default.is_a?(FalseClass) || default.is_a?(TrueClass) - assert type.is_a?(Boolean), "default value of param \"#{param_name}\" must be either true or false" - else - assert default.is_a?(type), "default value of param \"#{param_name}\" does not match type #{type}" - end - @@params[param_name] = default - @@defaults[param_name] = default - method_name = (param_name.to_s).to_sym - instance_eval <<-EOS - def #{method_name.to_s} - @@params[:#{param_name.to_s}] - end - EOS - instance_eval <<-EOS - def #{method_name.to_s}=(val) - @@params[:#{param_name.to_s}] = val - end - EOS - end - - def self.getConfig() - # get current time for random seed if set to "rand" - if @@params[:random_seed] == "rand" - t = Time.now - @@params[:random_seed] = t.usec.to_i - end - if ! @@params[:random_seed].is_a?(Integer) - raise TypeException - end - str = "System sys0 "+argv+"\n" - LibRubyObject.all.each { |obj| - if obj.is_a?(SetAssociativeCache) - obj.calculateLatency - end - } - str += LibRubyObject.printConstructors - #puts str.gsub('%',' ').gsub('#','\n') - return str - end - - def self.generateConfig() - puts getConfig - end - - def self.printIfacePorts() - @@iface_ports.each { |port| - print port.obj_name, " " - } - puts - end - - def self.getBochsConnections() - ports = Hash.new - @@iface_ports.each { |port| - ports[port.obj_name] = port.bochsConnType - } - return ports - end - - def self.getMemorySizeMB() - DirectoryMemory.memorySizeMB - end - - # override the default accessors (generated by default_param) for random_seed - def self.random_seed=(seed) - assert (val.is_a?(Integer) or val == "rand"), "RubySystem.random_seed takes either an integer value or the string \"rand\"" - @@params[:random_seed] = seed - end - -private - - def self.argv() - str = "" - @@params.each { |key, val| - str += key.id2name + " " - str += val.to_s + " " - } - return str - end - - def self.writeConfig() - @@network.printTopology - end - -end - -class CacheController < NetPort - - def initialize(obj_name, mach_type, caches) - super(obj_name, mach_type) - caches.each { |cache| - cache.controller = self - } - end - - def cppClassName() - "generated:"+@mach_type - end -end - -class Sequencer < IfacePort -end - -class L1CacheController < CacheController - param :sequencer, Sequencer - - def initialize(obj_name, mach_type, caches, sequencer) - super(obj_name, mach_type, caches) - - sequencer.controller = self - sequencer.version = version - self.sequencer= sequencer - end - -# def argv() -# vec = super() -# vec += " sequencer "+@sequencer.obj_name -# end -end - -class DirectoryMemory < LibRubyObject -end -class MemoryControl < LibRubyObject -end - -class DirectoryController < NetPort - @@total_directory_controllers = 0 - param :directory, DirectoryMemory - param :memory_control, MemoryControl - - def initialize(obj_name, mach_type, directory, memory_control) - super(obj_name, mach_type) - - directory.controller = self - directory.version = @@total_directory_controllers - self.directory = directory - self.memory_control = memory_control - - @version = @@total_directory_controllers - @@total_directory_controllers += 1 - buffer_size() - end - - def cppClassName() - "generated:"+@mach_type - end - -end - -class DMASequencer < IfacePort -end - -class DMAController < NetPort - @@total_dma_controllers = 0 - param :dma_sequencer, DMASequencer - param :version, Integer - - def initialize(obj_name, mach_type, dma_sequencer) - super(obj_name, mach_type) - dma_sequencer.controller = self - dma_sequencer.version = @@total_dma_controllers - self.dma_sequencer = dma_sequencer - - self.version = @@total_dma_controllers - @@total_dma_controllers += 1 - end - -end - -class Cache < LibRubyObject - param :size, Integer - param :latency, Integer - param :controller, NetPort - def initialize(obj_name, size, latency) - super(obj_name) - self.size = size - self.latency = latency - # controller must be set manually by the configuration script - # because there is a cyclic dependence - end - -end - -class SetAssociativeCache < Cache - param :assoc, Integer - param :replacement_policy, String - - # latency can be either an integer, a float, or the string "auto" - # when an integer, it represents the number of cycles for a hit - # when a float, it represents the cache access time in ns - # when set to "auto", libruby will attempt to find a realistic latency by running CACTI - def initialize(obj_name, size, latency, assoc, replacement_policy) - super(obj_name, size, latency) - self.assoc = assoc - self.replacement_policy = replacement_policy - end - - def calculateLatency() - if self.latency == "auto" - cacti_args = Array.new() - cacti_args << (self.size*1024) << RubySystem.block_size_bytes << self.assoc - cacti_args << 1 << 0 << 0 << 0 << 1 - cacti_args << RubySystem.tech_nm << RubySystem.block_size_bytes*8 - cacti_args << 0 << 0 << 0 << 1 << 0 << 0 << 0 << 0 << 1 - cacti_args << 360 << 0 << 0 << 0 << 0 << 1 << 1 << 1 << 1 << 0 << 0 - cacti_args << 50 << 10 << 10 << 0 << 1 << 1 - - cacti_cmd = File.dirname(__FILE__) + "/cacti/cacti " + cacti_args.join(" ") - - IO.popen(cacti_cmd) { |pipe| - str1 = pipe.readline - str2 = pipe.readline - results = str2.split(", ") - if results.size != 61 - print "CACTI ERROR: CACTI produced unexpected output.\n" - print "Are you using the version shipped with libruby?\n" - raise Exception - end - latency_ns = results[5].to_f - if (latency_ns == "1e+39") - print "CACTI ERROR: CACTI was unable to realistically model the cache ",@obj_name,"\n" - print "Either change the cache parameters or manually set the latency values\n" - raise Exception - end - clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6)) - latency_cycles = (latency_ns / clk_period_ns).ceil - self.latency = latency_cycles - } - elsif self.latency.is_a?(Float) - clk_period_ns = 1e9 * (1.0 / (RubySystem.freq_mhz * 1e6)) - latency_cycles = (self.latency / clk_period_ns).ceil - self.latency = latency_cycles - elsif ! self.latency.is_a?(Integer) - raise Exception - end - end - - def cppClassName() - "SetAssociativeCache" - end -end - -class DirectoryMemory < LibRubyObject - param :size_mb, Integer - param :controller, NetPort - param :version, Integer - - @@total_size_mb = 0 - - def initialize(obj_name, size_mb) - super(obj_name) - self.size_mb = size_mb - @@total_size_mb += size_mb - end - - def cppClassName() - "DirectoryMemory" - end - - def self.memorySizeMB() - @@total_size_mb - end -end - -class MemoryControl < LibRubyObject - def initialize(obj_name) - super(obj_name) - end - - def cppClassName() - "MemoryControl" - end -end - - -class Sequencer < IfacePort - - def cppClassName() - "Sequencer" - end - - param :controller, NetPort # must be set after initialization - param :icache, Cache - param :dcache, Cache - param :version, Integer - - def initialize(obj_name, icache, dcache) - super(obj_name) - self.icache=icache - self.dcache=dcache - end - - def bochsConnType() - return "cpu"+version.to_s - end - -end - - - -class DMASequencer < IfacePort - param :controller, NetPort - param :version, Integer - - def initialize(obj_name) - super(obj_name) - end - - def cppClassName() - "DMASequencer" - end - - def bochsConnType() - return "dma"+self.version.to_s - end -end - -class IntNode - @@num = 0 - def initialize() - - end -end - -class Network < LibRubyObject -end - -class Topology < LibRubyObject - attr :net_ports - param :network, Network - def initialize(name, net_ports) - super(name) - @net_ports = net_ports - end - - def cppClassName - "Topology" - end -end - -class Network < LibRubyObject - param :topology, Topology - def initialize(name, topo) - super(name) - topo.network= self - self.topology = topo - end - - def printTopology() - topology().printFile - end - def cppClassName() - "SimpleNetwork" - end - -end - -class PtToPtTopology < Topology - - param :connections,String - - def initialize(name, net_ports) - super(name, net_ports) - @params[:connections] = "" - @net_ports.each_index { |idx| - @params[:connections] << ("ext_node:"+@net_ports[idx].port_name+":"+@net_ports[idx].port_num.to_s) - @params[:connections] << ("%int_node:"+ idx.to_s+ "%link_latency:"+ link_latency.to_s) - @params[:connections] << ("%bw_multiplier:"+external_bw.to_s+"#") - } - @net_ports.each_index { |outer_idx| - @net_ports.each_index { |inner_idx| - if (outer_idx != inner_idx) - @params[:connections] << ("int_node:"+ outer_idx.to_s+ "%int_node:"+ inner_idx.to_s) - @params[:connections] << ("%link_latency:"+link_latency.to_s+"%bw_multiplier:"+internal_bw.to_s) - @params[:connections] << ("%link_weight:"+1.to_s+"#") - end - } - } - # call the accessors of the parent class to initialize them - # need to find a better method!! - print_config - end - -end - -class CrossbarTopology < Topology - param :connections,String - - def initialize(name, net_ports) - super(name, net_ports) - @params[:connections] = "" - crossbar_node = @net_ports.size - @net_ports.each_index { |idx| - @params[:connections] << ("ext_node:"+@net_ports[idx].port_name+":"+@net_ports[idx].port_num.to_s) - @params[:connections] << ("%int_node:"+ idx.to_s+ "%link_latency:"+ link_latency.to_s) - @params[:connections] << ("%bw_multiplier:"+external_bw.to_s+"#") - } - @net_ports.each_index { |idx| - @params[:connections] << ("int_node:"+idx.to_s+"%int_node:"+crossbar_node.to_s) - @params[:connections] << ("%link_latency:"+link_latency.to_s+"%bw_multiplier:"+internal_bw.to_s) - @params[:connections] << ("%link_weight:"+1.to_s+"#") - } - print_config - end -end - -class Tracer < LibRubyObject - def initialize(obj_name) - super(obj_name) - end - - def cppClassName() - "Tracer" - end - -end - -class Profiler < LibRubyObject - def initialize(obj_name) - super(obj_name) - end - - def cppClassName() - "Profiler" - end - -end - -class GarnetNetwork < Network - def initialize(name, topo) - super(name, topo) - end -end - -class GarnetFixedPipeline < GarnetNetwork - def initialize(name, net_ports) - super(name, net_ports) - end - - def cppClassName() - "GarnetNetwork_d" - end -end - -class GarnetFlexiblePipeline < GarnetNetwork - def initialize(name, net_ports) - super(name, net_ports) - end - - def cppClassName() - "GarnetNetwork" - end -end - -require "defaults.rb" diff --git a/src/mem/ruby/config/defaults.rb b/src/mem/ruby/config/defaults.rb deleted file mode 100644 index 224bf1eeb..000000000 --- a/src/mem/ruby/config/defaults.rb +++ /dev/null @@ -1,248 +0,0 @@ -#!/usr/bin/ruby - -class NetPort < LibRubyObject - # number of transitions a SLICC state machine can transition per - # cycle - default_param :transitions_per_cycle, Integer, 32 - - # buffer_size limits the size of all other buffers connecting to - # SLICC Controllers. When 0, infinite buffering is used. - default_param :buffer_size, Integer, 32 - - default_param :number_of_TBEs, Integer, 256 - - default_param :recycle_latency, Integer, 10 -end - -class Sequencer < IfacePort - # Maximum number of requests (including prefetches) outstanding from - # the sequencer - default_param :max_outstanding_requests, Integer, 16 - - # Maximum number of cycles a request is can be outstanding before - # the Sequencer declares we're in deadlock/livelock - default_param :deadlock_threshold, Integer, 500000 - -end - -class Debug < LibRubyObject - # For debugging purposes, one can enable a trace of all the protocol - # state machine changes. Unfortunately, the code to generate the - # trace is protocol specific. To enable the code for some of the - # standard protocols, - # 1. change protocol_trace = true - # 2. enable debug in the Ruby Makefile - # 3. set start_time = 1 - default_param :protocol_trace, Boolean, false - - # a string for filtering debugging output. Valid options (also see Debug.cc): - # {"System", 's' }, - # {"Node", 'N' }, - # {"Queue", 'q' }, - # {"Event Queue", 'e' }, - # {"Network", 'n' }, - # {"Sequencer", 'S' }, - # {"Tester", 't' }, - # {"Generated", 'g' }, - # {"SLICC", 'l' }, - # {"Network Queues", 'Q' }, - # {"Time", 'T' }, - # {"Network Internals", 'i' }, - # {"Store Buffer", 'b' }, - # {"Cache", 'c' }, - # {"Predictor", 'p' }, - # {"Allocator", 'a' } - # - # e.g., "sq" will print system and queue debugging messages - # Set to "none" for no debugging output - default_param :filter_string, String, "none" - - # filters debugging messages based on priority (none, low, med, high) - default_param :verbosity_string, String, "none" - - # filters debugging messages based on a ruby time - default_param :start_time, Integer, 1 - - # sends debugging messages to a output filename - # set to "none" to print to stdout - default_param :output_filename, String, "none" -end - -class Topology < LibRubyObject - # The default link latency between all nodes (internal and external) - # in the toplogy - default_param :link_latency, Integer, 1 - - # the bandwidth from an external network port to it's corresponding - # internal switch - default_param :external_bw, Integer, 64 - - # the bandwitch between internal switches in the network - default_param :internal_bw, Integer, 16 - - # indicates whether the topology config will be displayed in the - # stats file - default_param :print_config, Boolean, false -end - -class Network < LibRubyObject - default_param :endpoint_bandwidth, Integer, 10000 - default_param :adaptive_routing, Boolean, true - default_param :number_of_virtual_networks, Integer, 5 - # default_param :fan_out_degree, Integer, 4 - - # default buffer size. Setting to 0 indicates infinite buffering - # default_param :buffer_size, Integer, 0 - - # local memory latency ?? NetworkLinkLatency - default_param :link_latency, Integer, 1 - - # on chip latency - # default_param :on_chip_latency, Integer, 1 - - default_param :control_msg_size, Integer, 8 -end - -class GarnetNetwork < Network - default_param :flit_size, Integer, 16 - default_param :number_of_pipe_stages, Integer, 4 - default_param :vcs_per_class, Integer, 4 - default_param :buffer_size, Integer, 4 - default_param :using_network_testing, Boolean, false -end - -class Tracer < LibRubyObject - default_param :warmup_length, Integer, 1000000 -end - -class Profiler < LibRubyObject - default_param :hot_lines, Boolean, false - default_param :all_instructions, Boolean, false -end - -class MemoryControl < LibRubyObject - - default_param :mem_bus_cycle_multiplier, Integer, 10 - default_param :banks_per_rank, Integer, 8 - default_param :ranks_per_dimm, Integer, 2 - default_param :dimms_per_channel, Integer, 2 - default_param :bank_bit_0, Integer, 8 - default_param :rank_bit_0, Integer, 11 - default_param :dimm_bit_0, Integer, 12 - default_param :bank_queue_size, Integer, 12 - default_param :bank_busy_time, Integer, 11 - default_param :rank_rank_delay, Integer, 1 - default_param :read_write_delay, Integer, 2 - default_param :basic_bus_busy_time, Integer, 2 - default_param :mem_ctl_latency, Integer, 12 - default_param :refresh_period, Integer, 1560 - default_param :tFaw, Integer, 0 - default_param :mem_random_arbitrate, Integer, 11 - default_param :mem_fixed_delay, Integer, 0 - -end - -###### Protocols ####### - -## MI_example protocol - -class MI_example_CacheController < L1CacheController - default_param :issue_latency, Integer, 2 - default_param :cache_response_latency, Integer, 12 -end - -class MI_example_DirectoryController < DirectoryController - default_param :directory_latency, Integer, 6 -end - -class MI_example_DMAController < DMAController - default_param :request_latency, Integer, 6 -end - -## MOESI_CMP_directory protocol - -class MOESI_CMP_directory_L1CacheController < L1CacheController - default_param :request_latency, Integer, 2 -end - -class MOESI_CMP_directory_L2CacheController < CacheController - default_param :request_latency, Integer, 2 - default_param :response_latency, Integer, 2 -end - -class MOESI_CMP_directory_DirectoryController < DirectoryController - default_param :directory_latency, Integer, 6 -end - -class MOESI_CMP_directory_DMAController < DMAController - default_param :request_latency, Integer, 14 - default_param :response_latency, Integer, 14 -end - -class MESI_CMP_directory_L2CacheController < CacheController - default_param :request_latency, Integer, 2 - default_param :response_latency, Integer, 2 - default_param :to_L1_latency, Integer, 1 - -#if 0 then automatically calculated - default_param :lowest_bit, Integer, 0 - default_param :highest_bit, Integer, 0 -end - -class MESI_CMP_directory_L1CacheController < L1CacheController - default_param :l1_request_latency, Integer, 2 - default_param :l1_response_latency, Integer, 2 - default_param :to_L2_latency, Integer, 1 -end - - -class MESI_CMP_directory_DirectoryController < DirectoryController - default_param :to_mem_ctrl_latency, Integer, 1 - default_param :directory_latency, Integer, 6 -end - -class MESI_CMP_directory_DMAController < DMAController - default_param :request_latency, Integer, 6 -end - -class RubySystem - - # Random seed used by the simulation. If set to "rand", the seed - # will be set to the current wall clock at libruby - # initialization. Otherwise, set this to an integer. - default_param :random_seed, Object, 1234 #"rand" - - # When set to true, the simulation will insert random delays on - # message enqueue times. Note that even if this is set to false, - # you can still have a non-deterministic simulation if random seed - # is set to "rand". This is used mainly to debug protocols by forcing - # really strange interleavings and should not be used for - # performance runs. - default_param :randomization, Boolean, false - - # tech_nm is the device size used to calculate latency and area - # information about system components - default_param :tech_nm, Integer, 45 - - # default frequency for the system - default_param :freq_mhz, Integer, 3000 - - # the default cache block size in the system - # libruby does not currently support different block sizes - # among different caches - # Must be a power of two - default_param :block_size_bytes, Integer, 64 - - # The default debug object. There shouldn't be a reason to ever - # change this line. To adjust debug paramters statically, adjust - # them in the Debug class above. To adjust these fields - # dynamically, access this RubySystem object, - # e.g. RubySystem.debug.protocol_trace = true - default_param :debug, Debug, Debug.new("dbg0") - default_param :tracer, Tracer, Tracer.new("tracer0") - - default_param :profiler, Profiler, Profiler.new("profiler0") -end - - - diff --git a/src/mem/ruby/config/libruby_cfg_test.cc b/src/mem/ruby/config/libruby_cfg_test.cc deleted file mode 100644 index 5d5b69d5f..000000000 --- a/src/mem/ruby/config/libruby_cfg_test.cc +++ /dev/null @@ -1,14 +0,0 @@ - -#include <iostream> -#include <assert.h> - -#include "../libruby.hh" - -int main(int argc, char* argv[]) -{ - assert(argc == 2); - const char* cfg_file = argv[1]; - - libruby_init(cfg_file); - libruby_print_config(std::cout); -} diff --git a/src/mem/ruby/config/print_cfg.rb b/src/mem/ruby/config/print_cfg.rb deleted file mode 100644 index 0a6d180d4..000000000 --- a/src/mem/ruby/config/print_cfg.rb +++ /dev/null @@ -1,14 +0,0 @@ - -ruby_cfg_file = nil -$stderr.puts $*.inspect -for i in 0..$*.size-1 do - if $*[i] == "-r" # ruby config file - i += 1 - ruby_cfg_file = $*[i] - break - end -end - -require ruby_cfg_file - -RubySystem.generateConfig diff --git a/src/mem/ruby/config/util.rb b/src/mem/ruby/config/util.rb deleted file mode 100644 index a6aa8f6ab..000000000 --- a/src/mem/ruby/config/util.rb +++ /dev/null @@ -1,10 +0,0 @@ - -def log_int(n) - assert(n.is_a?(Fixnum), "log_int takes a number for an argument") - counter = 0 - while n >= 2 do - counter += 1 - n = n >> 1 - end - return counter -end |