diff options
Diffstat (limited to 'src/mem/ruby/config')
| -rw-r--r-- | src/mem/ruby/config/MI_example-homogeneous.rb | 15 | ||||
| -rw-r--r-- | src/mem/ruby/config/MI_example.rb | 35 | ||||
| -rw-r--r-- | src/mem/ruby/config/MOESI_CMP_directory.rb | 79 | ||||
| -rw-r--r-- | src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb | 98 | ||||
| -rw-r--r-- | src/mem/ruby/config/cfg.rb | 81 | ||||
| -rw-r--r-- | src/mem/ruby/config/defaults.rb | 50 |
6 files changed, 297 insertions, 61 deletions
diff --git a/src/mem/ruby/config/MI_example-homogeneous.rb b/src/mem/ruby/config/MI_example-homogeneous.rb index d43e384e5..451281f20 100644 --- a/src/mem/ruby/config/MI_example-homogeneous.rb +++ b/src/mem/ruby/config/MI_example-homogeneous.rb @@ -17,11 +17,16 @@ L1_CACHE_LATENCY = 1 num_memories = 2 memory_size_mb = 1024 NUM_DMA = 1 +protocol = "MI_example" # check for overrides + for i in 0..$*.size-1 do - if $*[i] == "-p" + if $*[i] == "-c" + protocol = $*[i+1] + i = i+1 + elsif $*[i] == "-p" num_cores = $*[i+1].to_i i = i+1 elsif $*[i] == "-m" @@ -36,13 +41,17 @@ end net_ports = Array.new iface_ports = Array.new +assert(protocol == "MI_example", __FILE__ + " cannot be used with protocol " + protocol) + +require protocol+".rb" + num_cores.times { |n| cache = SetAssociativeCache.new("l1u_"+n.to_s, L1_CACHE_SIZE_KB, L1_CACHE_LATENCY, L1_CACHE_ASSOC, "PSEUDO_LRU") sequencer = Sequencer.new("Sequencer_"+n.to_s, cache, cache) iface_ports << sequencer net_ports << MI_example_CacheController.new("L1CacheController_"+n.to_s, "L1Cache", - [cache], + cache, sequencer) } num_memories.times { |n| @@ -55,7 +64,7 @@ num_memories.times { |n| NUM_DMA.times { |n| dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s) iface_ports << dma_sequencer - net_ports << DMAController.new("DMAController_"+n.to_s, "DMA", dma_sequencer) + net_ports << MI_example_DMAController.new("DMAController_"+n.to_s, "DMA", dma_sequencer) } topology = CrossbarTopology.new("theTopology", net_ports) diff --git a/src/mem/ruby/config/MI_example.rb b/src/mem/ruby/config/MI_example.rb new file mode 100644 index 000000000..3196bb639 --- /dev/null +++ b/src/mem/ruby/config/MI_example.rb @@ -0,0 +1,35 @@ + +class MI_example_CacheController < L1CacheController + attr :cache + def initialize(obj_name, mach_type, cache, sequencer) + super(obj_name, mach_type, [cache], sequencer) + @cache = cache + end + def argv() + vec = super() + vec += " cache " + @cache.obj_name + vec += " issue_latency "+issue_latency.to_s + vec += " cache_response_latency "+cache_response_latency.to_s + end + +end + +class MI_example_DirectoryController < DirectoryController + def initialize(obj_name, mach_type, directory, memory_control) + super(obj_name, mach_type, directory, memory_control) + end + def argv() + vec = super() + vec += " directory_latency "+directory_latency.to_s + end +end + +class MI_example_DMAController < DMAController + def initialize(obj_name, mach_type, dma_sequencer) + super(obj_name, mach_type, dma_sequencer) + end + def argv() + vec = super + vec += " request_latency "+request_latency.to_s + end +end diff --git a/src/mem/ruby/config/MOESI_CMP_directory.rb b/src/mem/ruby/config/MOESI_CMP_directory.rb new file mode 100644 index 000000000..936eb8e80 --- /dev/null +++ b/src/mem/ruby/config/MOESI_CMP_directory.rb @@ -0,0 +1,79 @@ + +require "cfg.rb" + +def log_int(n) + assert(n.is_a?(Fixnum), "log_int takes a number for an argument") + counter = 0 + while n >= 2 do + counter += 1 + n = n >> 1 + end + return counter +end + + +class MOESI_CMP_directory_L1CacheController < L1CacheController + attr :icache, :dcache + attr :num_l2_controllers + def initialize(obj_name, mach_type, icache, dcache, sequencer, num_l2_controllers) + super(obj_name, mach_type, [icache, dcache], sequencer) + @icache = icache + @dcache = dcache + @num_l2_controllers = num_l2_controllers + end + def argv() + num_select_bits = log_int(num_l2_controllers) + num_block_bits = log_int(RubySystem.block_size_bytes) + + l2_select_low_bit = num_block_bits + l2_select_high_bit = num_block_bits + num_select_bits - 1 + + vec = super() + vec += " icache " + @icache.obj_name + vec += " dcache " + @dcache.obj_name + vec += " request_latency "+request_latency().to_s + vec += " l2_select_low_bit " + l2_select_low_bit.to_s + vec += " l2_select_high_bit " + l2_select_high_bit.to_s + return vec + end +end + +class MOESI_CMP_directory_L2CacheController < CacheController + attr :cache + def initialize(obj_name, mach_type, cache) + super(obj_name, mach_type, [cache]) + @cache = cache + end + def argv() + vec = super() + vec += " cache " + @cache.obj_name + vec += " request_latency "+request_latency().to_s + vec += " response_latency "+response_latency().to_s + return vec + end +end + + +class MOESI_CMP_directory_DirectoryController < DirectoryController + def initialize(obj_name, mach_type, directory, memory_control) + super(obj_name, mach_type, directory, memory_control) + end + def argv() + vec = super() + vec += " directory_latency "+directory_latency.to_s + return vec + end + +end + +class MOESI_CMP_directory_DMAController < DMAController + def initialize(obj_name, mach_type, dma_sequencer) + super(obj_name, mach_type, dma_sequencer) + end + def argv() + vec = super + vec += " request_latency "+request_latency.to_s + vec += " response_latency "+response_latency.to_s + return vec + end +end diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb new file mode 100644 index 000000000..11cb7fb57 --- /dev/null +++ b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb @@ -0,0 +1,98 @@ +#!/usr/bin/ruby +# +# Creates a homogeneous CMP system with a single unified cache per +# core and a crossbar network. Uses the default parameters listed +# below, which can be overridden using command line args. +# + +require "cfg.rb" + +# default values + +num_cores = 2 +L1_ICACHE_SIZE_KB = 32 +L1_ICACHE_ASSOC = 8 +L1_ICACHE_LATENCY = 1 +L1_DCACHE_SIZE_KB = 32 +L1_DCACHE_ASSOC = 8 +L1_DCACHE_LATENCY = 1 +L2_CACHE_SIZE_KB = 2048 # total size (sum of all banks) +L2_CACHE_ASSOC = 16 +L2_CACHE_LATENCY = 12 +num_l2_banks = num_cores +num_memories = 1 +memory_size_mb = 1024 +NUM_DMA = 1 + +protocol = "MOESI_CMP_directory" + +# check for overrides + +for i in 0..$*.size-1 do + if $*[i] == "-c" or $*[i] == "--protocol" + i += 1 + protocol = $*[i] + elsif $*[i] == "-m" + num_memories = $*[i+1].to_i + i = i+1 + elsif $*[i] == "-p" + num_cores = $*[i+1].to_i + i = i+1 + elsif $*[i] == "-s" + memory_size_mb = $*[i+1].to_i + i = i + 1 + end +end + +net_ports = Array.new +iface_ports = Array.new + +assert(protocol == "MOESI_CMP_directory", __FILE__+" cannot be used with protocol "+protocol); + +require protocol+".rb" + +num_cores.times { |n| + icache = SetAssociativeCache.new("l1i_"+n.to_s, L1_ICACHE_SIZE_KB, L1_ICACHE_LATENCY, L1_ICACHE_ASSOC, "PSEUDO_LRU") + dcache = SetAssociativeCache.new("l1d_"+n.to_s, L1_DCACHE_SIZE_KB, L1_DCACHE_LATENCY, L1_DCACHE_ASSOC, "PSEUDO_LRU") + sequencer = Sequencer.new("Sequencer_"+n.to_s, icache, dcache) + iface_ports << sequencer + if protocol == "MOESI_CMP_directory" + net_ports << MOESI_CMP_directory_L1CacheController.new("L1CacheController_"+n.to_s, + "L1Cache", + icache, dcache, + sequencer, + num_l2_banks) + end +} +num_l2_banks.times { |n| + cache = SetAssociativeCache.new("l2u_"+n.to_s, L2_CACHE_SIZE_KB/num_l2_banks, L2_CACHE_LATENCY, L2_CACHE_ASSOC, "PSEUDO_LRU") + if protocol == "MOESI_CMP_directory" + net_ports << MOESI_CMP_directory_L2CacheController.new("L2CacheController_"+n.to_s, + "L2Cache", + cache) + end +} +num_memories.times { |n| + directory = DirectoryMemory.new("DirectoryMemory_"+n.to_s, memory_size_mb/num_memories) + memory_control = MemoryControl.new("MemoryControl_"+n.to_s) + if protocol == "MOESI_CMP_directory" + net_ports << MOESI_CMP_directory_DirectoryController.new("DirectoryController_"+n.to_s, + "Directory", + directory, + memory_control) + end +} +NUM_DMA.times { |n| + dma_sequencer = DMASequencer.new("DMASequencer_"+n.to_s) + iface_ports << dma_sequencer + if protocol == "MOESI_CMP_directory" + net_ports << MOESI_CMP_directory_DMAController.new("DMAController_"+n.to_s, + "DMA", + dma_sequencer) + end +} + +topology = CrossbarTopology.new("theTopology", net_ports) +on_chip_net = Network.new("theNetwork", topology) + +RubySystem.init(iface_ports, on_chip_net) diff --git a/src/mem/ruby/config/cfg.rb b/src/mem/ruby/config/cfg.rb index a43b5e125..82fbb64a5 100644 --- a/src/mem/ruby/config/cfg.rb +++ b/src/mem/ruby/config/cfg.rb @@ -233,6 +233,7 @@ class RubySystem end } str += LibRubyObject.printConstructors + #puts str.gsub('%',' ').gsub('#','\n') return str end @@ -287,35 +288,33 @@ end class CacheController < NetPort - @@total_cache_controllers = 0 - attr :caches - attr :sequencer - def initialize(obj_name, mach_type, caches, sequencer) + @@total_cache_controllers = Hash.new + + def initialize(obj_name, mach_type, caches) super(obj_name, mach_type) - @caches = caches - @caches.each { |cache| + caches.each { |cache| cache.controller = self } - @sequencer = sequencer - @sequencer.controller = self - - @version = @@total_cache_controllers - @@total_cache_controllers += 1 - @sequencer.version = @version - buffer_size() + if !@@total_cache_controllers.has_key?(mach_type) + @@total_cache_controllers[mach_type] = 0 + end + @version = @@total_cache_controllers[mach_type] + @@total_cache_controllers[mach_type] += 1 + + # call inhereted parameters + transitions_per_cycle + buffer_size + number_of_TBEs + recycle_latency end def argv() vec = "version "+@version.to_s - @caches.each { |cache| - vec += " cache " + cache.obj_name - } - vec += " sequencer "+@sequencer.obj_name vec += " transitions_per_cycle "+@params[:transitions_per_cycle].to_s vec += " buffer_size "+@params[:buffer_size].to_s vec += " number_of_TBEs "+@params[:number_of_TBEs].to_s - + vec += " recycle_latency "+@params[:recycle_latency].to_s end def cppClassName() @@ -323,6 +322,23 @@ class CacheController < NetPort end end +class L1CacheController < CacheController + attr :sequencer + + def initialize(obj_name, mach_type, caches, sequencer) + super(obj_name, mach_type, caches) + + @sequencer = sequencer + @sequencer.controller = self + @sequencer.version = @version + end + + def argv() + vec = super() + vec += " sequencer "+@sequencer.obj_name + end +end + class DirectoryController < NetPort @@total_directory_controllers = 0 attr :directory @@ -364,7 +380,7 @@ class DMAController < NetPort end def argv() - "version "+@version.to_s+" dma_sequencer "+@dma_sequencer.obj_name+" transitions_per_cycle "+@params[:transitions_per_cycle].to_s + " buffer_size "+@params[:buffer_size].to_s + " number_of_TBEs "+@params[:number_of_TBEs].to_s + "version "+@version.to_s+" dma_sequencer "+@dma_sequencer.obj_name+" transitions_per_cycle "+@params[:transitions_per_cycle].to_s + " buffer_size "+@params[:buffer_size].to_s + " number_of_TBEs "+@params[:number_of_TBEs].to_s + " recycle_latency "+@params[:recycle_latency].to_s end def cppClassName() @@ -606,7 +622,7 @@ class Network < LibRubyObject end def printTopology() - topology.printFile + topology().printFile end def cppClassName() "SimpleNetwork" @@ -686,31 +702,6 @@ class Profiler < LibRubyObject end -class MI_example_CacheController < CacheController - def initialize(obj_name, mach_type, caches, sequencer) - super(obj_name, mach_type, caches, sequencer) - end - def argv() - vec = super() - vec += " issue_latency "+issue_latency.to_s - vec += " cache_response_latency "+cache_response_latency.to_s - end - -end - -class MI_example_DirectoryController < DirectoryController - def initialize(obj_name, mach_type, directory, memory_control) - super(obj_name, mach_type, directory, memory_control) - end - def argv() - vec = super() - vec += " to_mem_ctrl_latency "+to_mem_ctrl_latency.to_s - vec += " directory_latency "+directory_latency.to_s - vec += " memory_latency "+memory_latency.to_s - end - -end - #added by SS class GarnetNetwork < Network def initialize(name, topo) diff --git a/src/mem/ruby/config/defaults.rb b/src/mem/ruby/config/defaults.rb index e54b148e0..4723df505 100644 --- a/src/mem/ruby/config/defaults.rb +++ b/src/mem/ruby/config/defaults.rb @@ -106,19 +106,6 @@ class Profiler < LibRubyObject end #added by SS -class MI_example_CacheController < CacheController - default_param :issue_latency, Integer, 2 - default_param :cache_response_latency, Integer, 12 -end - -class MI_example_DirectoryController < DirectoryController - default_param :to_mem_ctrl_latency, Integer, 1 - default_param :directory_latency, Integer, 6 - default_param :memory_latency, Integer, 158 -end - - -#added by SS class MemoryControl < LibRubyObject default_param :mem_bus_cycle_multiplier, Integer, 10 @@ -141,6 +128,43 @@ class MemoryControl < LibRubyObject end +###### Protocols ####### + +## MI_example protocol + +class MI_example_CacheController < L1CacheController + default_param :issue_latency, Integer, 2 + default_param :cache_response_latency, Integer, 12 +end + +class MI_example_DirectoryController < DirectoryController + default_param :directory_latency, Integer, 6 +end + +class MI_example_DMAController < DMAController + default_param :request_latency, Integer, 6 +end + +## MOESI_CMP_directory protocol + +class MOESI_CMP_directory_L1CacheController < L1CacheController + default_param :request_latency, Integer, 2 +end + +class MOESI_CMP_directory_L2CacheController < CacheController + default_param :request_latency, Integer, 2 + default_param :response_latency, Integer, 2 +end + +class MOESI_CMP_directory_DirectoryController < DirectoryController + default_param :directory_latency, Integer, 6 +end + +class MOESI_CMP_directory_DMAController < DMAController + default_param :request_latency, Integer, 6 + default_param :response_latency, Integer, 6 +end + class RubySystem # Random seed used by the simulation. If set to "rand", the seed |