1 files changed, 9 insertions, 9 deletions

diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
index 07c6bec3a..de2e3d67f 100644
--- a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
@@ -56,18 +56,18 @@ class InputUnit_d : public Consumer
     inline int get_inlink_id() { return m_in_link->get_id(); }
 
     inline void
-    set_vc_state(VC_state_type state, int vc, Time curTime)
+    set_vc_state(VC_state_type state, int vc, Cycles curTime)
     {
         m_vcs[vc]->set_state(state, curTime);
     }
 
     inline void
-    set_enqueue_time(int invc, Time time)
+    set_enqueue_time(int invc, Cycles time)
     {
         m_vcs[invc]->set_enqueue_time(time);
     }
 
-    inline Time
+    inline Cycles
     get_enqueue_time(int invc)
     {
         return m_vcs[invc]->get_enqueue_time();
@@ -86,7 +86,7 @@ class InputUnit_d : public Consumer
     }
 
     inline void
-    increment_credit(int in_vc, bool free_signal, Time curTime)
+    increment_credit(int in_vc, bool free_signal, Cycles curTime)
     {
         flit_d *t_flit = new flit_d(in_vc, free_signal, curTime);
         creditQueue->insert(t_flit);
@@ -100,14 +100,14 @@ class InputUnit_d : public Consumer
     }
 
     inline void
-    updateRoute(int vc, int outport, Time curTime)
+    updateRoute(int vc, int outport, Cycles curTime)
     {
         m_vcs[vc]->set_outport(outport);
         m_vcs[vc]->set_state(VC_AB_, curTime);
     }
 
     inline void
-    grant_vc(int in_vc, int out_vc, Time curTime)
+    grant_vc(int in_vc, int out_vc, Cycles curTime)
     {
         m_vcs[in_vc]->grant_vc(out_vc, curTime);
     }
@@ -125,20 +125,20 @@ class InputUnit_d : public Consumer
     }
 
     inline bool
-    need_stage(int vc, VC_state_type state, flit_stage stage, Time curTime)
+    need_stage(int vc, VC_state_type state, flit_stage stage, Cycles curTime)
     {
         return m_vcs[vc]->need_stage(state, stage, curTime);
     }
 
     inline bool
     need_stage_nextcycle(int vc, VC_state_type state, flit_stage stage,
-                         Time curTime)
+                         Cycles curTime)
     {
         return m_vcs[vc]->need_stage_nextcycle(state, stage, curTime);
     }
 
     inline bool
-    isReady(int invc, Time curTime)
+    isReady(int invc, Cycles curTime)
     {
         return m_vcs[invc]->isReady(curTime);
     }