diff options
Diffstat (limited to 'src/mem/ruby/network/garnet')
8 files changed, 19 insertions, 13 deletions
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh index c188b12d6..6afb4726b 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh @@ -90,7 +90,7 @@ class InputUnit_d : public Consumer { flit_d *t_flit = new flit_d(in_vc, free_signal, curTime); creditQueue->insert(t_flit); - m_credit_link->scheduleEvent(Cycles(1)); + m_credit_link->scheduleEventAbsolute(m_router->clockEdge(Cycles(1))); } inline int diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc index bdae26fd0..e49216476 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc @@ -254,7 +254,8 @@ NetworkInterface_d::wakeup() flit_d *credit_flit = new flit_d(t_flit->get_vc(), free_signal, m_net_ptr->curCycle()); creditQueue->insert(credit_flit); - m_ni_credit_link->scheduleEvent(Cycles(1)); + m_ni_credit_link-> + scheduleEventAbsolute(m_net_ptr->clockEdge(Cycles(1))); int vnet = t_flit->get_vnet(); m_net_ptr->increment_received_flits(vnet); @@ -328,7 +329,8 @@ NetworkInterface_d::scheduleOutputLink() t_flit->set_time(m_net_ptr->curCycle() + Cycles(1)); outSrcQueue->insert(t_flit); // schedule the out link - outNetLink->scheduleEvent(Cycles(1)); + outNetLink-> + scheduleEventAbsolute(m_net_ptr->clockEdge(Cycles(1))); if (t_flit->get_type() == TAIL_ || t_flit->get_type() == HEAD_TAIL_) { diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc index afa9d63d3..d84bf8e69 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc @@ -70,7 +70,7 @@ NetworkLink_d::wakeup() flit_d *t_flit = link_srcQueue->getTopFlit(); t_flit->set_time(curCycle() + m_latency); linkBuffer->insert(t_flit); - link_consumer->scheduleEvent(m_latency); + link_consumer->scheduleEventAbsolute(clockEdge(m_latency)); m_link_utilized++; m_vc_load[t_flit->get_vc()]++; } diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh index 50497303c..48bf361a5 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh +++ b/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh @@ -84,7 +84,7 @@ class OutputUnit_d : public Consumer insert_flit(flit_d *t_flit) { m_out_buffer->insert(t_flit); - m_out_link->scheduleEvent(Cycles(1)); + m_out_link->scheduleEventAbsolute(m_router->clockEdge(Cycles(1))); } uint32_t functionalWrite(Packet *pkt); diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc index 44ca81802..fd4ce5389 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc +++ b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc @@ -135,13 +135,13 @@ Router_d::route_req(flit_d *t_flit, InputUnit_d *in_unit, int invc) void Router_d::vcarb_req() { - m_vc_alloc->scheduleEvent(Cycles(1)); + m_vc_alloc->scheduleEventAbsolute(clockEdge(Cycles(1))); } void Router_d::swarb_req() { - m_sw_alloc->scheduleEvent(Cycles(1)); + m_sw_alloc->scheduleEventAbsolute(clockEdge(Cycles(1))); } void @@ -154,7 +154,7 @@ void Router_d::update_sw_winner(int inport, flit_d *t_flit) { m_switch->update_sw_winner(inport, t_flit); - m_switch->scheduleEvent(Cycles(1)); + m_switch->scheduleEventAbsolute(clockEdge(Cycles(1))); } void diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc index 79e295601..870560af0 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc +++ b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc @@ -321,7 +321,8 @@ NetworkInterface::scheduleOutputLink() outSrcQueue->insert(t_flit); // schedule the out link - outNetLink->scheduleEvent(Cycles(1)); + outNetLink-> + scheduleEventAbsolute(m_net_ptr->clockEdge(Cycles(1))); return; } } diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc index cdcd5a622..9881d8063 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc +++ b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc @@ -140,7 +140,8 @@ NetworkLink::wakeup() flit *t_flit = link_srcQueue->getTopFlit(); t_flit->set_time(curCycle() + m_latency); linkBuffer->insert(t_flit); - link_consumer->scheduleEvent(m_latency); + link_consumer->scheduleEventAbsolute(clockEdge(m_latency)); + m_link_utilized++; m_vc_load[t_flit->get_vc()]++; } diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc b/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc index 98317818b..851ababc4 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc +++ b/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc @@ -139,7 +139,7 @@ Router::request_vc(int in_vc, int in_port, NetDest destination, m_in_vc_state[in_port][in_vc]->setState(VC_AB_, request_time); assert(request_time >= curCycle()); if (request_time > curCycle()) - m_vc_arbiter->scheduleEventAbsolute(request_time); + m_vc_arbiter->scheduleEventAbsolute(clockPeriod() * request_time); else vc_arbitrate(); } @@ -364,7 +364,9 @@ Router::scheduleOutputLinks() m_router_buffers[port][vc_tolookat]->getTopFlit(); t_flit->set_time(curCycle() + Cycles(1)); m_out_src_queue[port]->insert(t_flit); - m_out_link[port]->scheduleEvent(Cycles(1)); + + m_out_link[port]-> + scheduleEventAbsolute(clockEdge(Cycles(1))); break; // done for this port } } @@ -400,7 +402,7 @@ Router::check_arbiter_reschedule() for (int vc = 0; vc < m_num_vcs; vc++) { if (m_in_vc_state[port][vc]->isInState(VC_AB_, curCycle() + Cycles(1))) { - m_vc_arbiter->scheduleEvent(Cycles(1)); + m_vc_arbiter->scheduleEventAbsolute(clockEdge(Cycles(1))); return; } } |