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Diffstat (limited to 'src/mem/ruby/network/orion/router.cfg')
| -rw-r--r-- | src/mem/ruby/network/orion/router.cfg | 146 |
1 files changed, 146 insertions, 0 deletions
diff --git a/src/mem/ruby/network/orion/router.cfg b/src/mem/ruby/network/orion/router.cfg new file mode 100644 index 000000000..68f0cd149 --- /dev/null +++ b/src/mem/ruby/network/orion/router.cfg @@ -0,0 +1,146 @@ +# Copyright (c) 2010 Massachusetts Institute of Technology +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Chia-Hsin Owen Chen + +# Technology related parameters +# technology node in nm (90, 65, 45, 32) +TECH_NODE = 65 +# transistor type (HVT, NVT, LVT) +TRANSISTOR_TYPE = NVT +# operating voltage supply in volt +VDD = 1.0 +# operating frequency in Hz +FREQUENCY = 1.0e9 + +# router module parameters +# general parameters +# number of router input ports +NUM_INPUT_PORT = 0 +# number of router output ports +NUM_OUTPUT_PORT = 0 +# flit width in bit +FLIT_WIDTH = 0 + +# virtual channel parameters +# number of message classes per port +NUM_VIRTUAL_CLASS = 0 +# number of virtual channels per message class +NUM_VIRTUAL_CHANNEL = 0 +# Are input virtual channels managed in a shared buffer? (Private buffer otherwise) +IS_IN_SHARED_BUFFER = FALSE +# Are output virtual channels managed in a shared buffer? (Private buffer otherwise) +IS_OUT_SHARED_BUFFER = FALSE +# Are input virtual channels sharing the same crossbar input ports? +IS_IN_SHARED_SWITCH = TRUE +# Are output virtual channels sharing the same crossbar output ports? +IS_OUT_SHARED_SWITCH = TRUE + +# crossbar parameters +# crossbar model +CROSSBAR_MODEL = MULTREE_CROSSBAR + +CROSSBAR_CONNECT_TYPE = TRISTATE_GATE +CROSSBAR_TRANS_GATE_TYPE = NP_GATE +CROSSBAR_MUX_DEGREE = 4 +CROSSBAR_NUM_IN_SEG = 1 +CROSSBAR_NUM_OUT_SEG = 1 +# crossbar input line length +CROSSBAR_LEN_IN_WIRE = 0 +# crossbar output line length +CROSSBAR_LEN_OUT_WIRE = 0 + +# input buffer parameters +IS_INPUT_BUFFER = TRUE +# input buffer model (SRAM, REGISTER) +IN_BUF_MODEL = REGISTER +IN_BUF_NUM_SET = 0 +IN_BUF_NUM_READ_PORT = 1 + +# output buffer parameters */ +IS_OUTPUT_BUFFER = FALSE +# output buffer model (SRAM, REGISTER) +OUT_BUF_MODEL = SRAM +OUT_BUF_NUM_SET = 0 +OUT_BUF_NUM_WRITE_PORT = 0 + +# array parameters shared by various sram buffers +SRAM_ROWDEC_MODEL = GENERIC_DEC +SRAM_ROWDEC_PRE_MODEL = SINGLE_OTHER +SRAM_WORDLINE_MODEL = RW_WORDLINE +SRAM_BITLINE_MODEL = RW_BITLINE +SRAM_OUTDRV_MODEL = REG_OUTDRV +# these 3 should be changed together +# use double-ended bitline because the array is too large +SRAM_NUM_DATA_END = 2 +SRAM_AMP_MODEL = GENERIC_AMP +SRAM_BITLINE_PRE_MODEL = EQU_BITLINE +# SRAM_NUM_DATA_END = 1 +# SRAM_AMP_MODEL = NO_MODEL +# SRAM_BITLINE_PRE_MODEL = SINGLE_OTHER + +# switch allocator arbiter parameters +# arbiter mode (MATRIX_ARBITER, RR_ARBITER) +SA_IN_ARB_MODEL = RR_ARBITER +# flip-flop model +SA_IN_ARB_FF_MODEL = NEG_DFF +# arbiter mode (MATRIX_ARBITER, RR_ARBITER) +SA_OUT_ARB_MODEL = MATRIX_ARBITER +# flip-flop model +SA_OUT_ARB_FF_MODEL = NEG_DFF + +# virtual channel allocator arbiter parameters +# allocator model (ONE_STAGE_ARB, TWO_STAGE_ARB, VC_SELECT) +VA_MODEL = TWO_STAGE_ARB +# arbiter mode (MATRIX_ARBITER, RR_ARBITER) +VA_IN_ARB_MODEL = RR_ARBITER +# flip-flop model +VA_IN_ARB_FF_MODEL = NEG_DFF +# arbiter mode (MATRIX_ARBITER, RR_ARBITER) +VA_OUT_ARB_MODEL = MATRIX_ARBITER +# flip-flop model +VA_OUT_ARB_FF_MODEL = NEG_DFF +# buffer model if VC_SELECT is used (SRAM, REGISTER) +VA_BUF_MODEL = REGISTER + +# link wire parameters +#link length in metres +LINK_LENGTH = 1e-3 +# wire layer model (INTERMEDIATE, GLOBAL) +WIRE_LAYER_TYPE = GLOBAL +# wire width spacing (SWIDTH_SSPACE, SWIDTH_DSPACE, DWIDTH_SSPACE, DWIDTH_DSPACE) +WIRE_WIDTH_SPACING = DWIDTH_DSPACE +# buffering model (MIN_DELAY, STAGGERED) +WIRE_BUFFERING_MODEL = MIN_DELAY +# is shielding +WIRE_IS_SHIELDING = FALSE + +# clock power parameters +NUM_PIPELINE_STAGE = 3 +IS_HTREE_CLOCK = FALSE +# router diagonal in um +ROUTER_DIAGONAL = 442 + |