diff options
Diffstat (limited to 'src/mem/ruby/network/simple')
| -rw-r--r-- | src/mem/ruby/network/simple/PerfectSwitch.cc | 7 | ||||
| -rw-r--r-- | src/mem/ruby/network/simple/SimpleNetwork.cc | 25 | ||||
| -rw-r--r-- | src/mem/ruby/network/simple/SimpleNetwork.hh | 3 | ||||
| -rw-r--r-- | src/mem/ruby/network/simple/SimpleNetwork.py | 40 | ||||
| -rw-r--r-- | src/mem/ruby/network/simple/Switch.cc | 23 | ||||
| -rw-r--r-- | src/mem/ruby/network/simple/Switch.hh | 3 | ||||
| -rw-r--r-- | src/mem/ruby/network/simple/Throttle.cc | 1 |
7 files changed, 65 insertions, 37 deletions
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc b/src/mem/ruby/network/simple/PerfectSwitch.cc index 06072724e..de038d211 100644 --- a/src/mem/ruby/network/simple/PerfectSwitch.cc +++ b/src/mem/ruby/network/simple/PerfectSwitch.cc @@ -76,13 +76,6 @@ PerfectSwitch::addInPort(const vector<MessageBuffer*>& in) for (int i = 0; i < in.size(); ++i) { if (in[i] != nullptr) { in[i]->setConsumer(this); - - string desc = - csprintf("[Queue from port %s %s %s to PerfectSwitch]", - to_string(m_switch_id), to_string(port), - to_string(i)); - - in[i]->setDescription(desc); in[i]->setIncomingLink(port); in[i]->setVnet(i); } diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc index 7426e9691..5b7d7ebad 100644 --- a/src/mem/ruby/network/simple/SimpleNetwork.cc +++ b/src/mem/ruby/network/simple/SimpleNetwork.cc @@ -62,6 +62,9 @@ SimpleNetwork::SimpleNetwork(const Params *p) m_switches.push_back(s); s->init_net_ptr(this); } + + m_int_link_buffers = p->int_link_buffers; + m_num_connected_buffers = 0; } void @@ -78,7 +81,7 @@ SimpleNetwork::init() SimpleNetwork::~SimpleNetwork() { deletePointers(m_switches); - deletePointers(m_buffers_to_free); + deletePointers(m_int_link_buffers); } // From a switch to an endpoint node @@ -121,16 +124,10 @@ SimpleNetwork::makeInternalLink(SwitchID src, SwitchID dest, BasicLink* link, for (int i = 0; i < m_virtual_networks; i++) { // allocate a buffer - MessageBuffer* buffer_ptr = new MessageBuffer; - buffer_ptr->setOrdering(true); - - if (m_buffer_size > 0) { - buffer_ptr->resize(m_buffer_size); - } - + assert(m_num_connected_buffers < m_int_link_buffers.size()); + MessageBuffer* buffer_ptr = m_int_link_buffers[m_num_connected_buffers]; + m_num_connected_buffers++; queues[i] = buffer_ptr; - // remember to deallocate it - m_buffers_to_free.push_back(buffer_ptr); } // Connect it to the two switches @@ -236,8 +233,8 @@ SimpleNetwork::functionalRead(Packet *pkt) } } - for (unsigned int i = 0; i < m_buffers_to_free.size(); ++i) { - if (m_buffers_to_free[i]->functionalRead(pkt)) { + for (unsigned int i = 0; i < m_int_link_buffers.size(); ++i) { + if (m_int_link_buffers[i]->functionalRead(pkt)) { return true; } } @@ -254,8 +251,8 @@ SimpleNetwork::functionalWrite(Packet *pkt) num_functional_writes += m_switches[i]->functionalWrite(pkt); } - for (unsigned int i = 0; i < m_buffers_to_free.size(); ++i) { - num_functional_writes += m_buffers_to_free[i]->functionalWrite(pkt); + for (unsigned int i = 0; i < m_int_link_buffers.size(); ++i) { + num_functional_writes += m_int_link_buffers[i]->functionalWrite(pkt); } return num_functional_writes; } diff --git a/src/mem/ruby/network/simple/SimpleNetwork.hh b/src/mem/ruby/network/simple/SimpleNetwork.hh index a2723c715..fe0c1838b 100644 --- a/src/mem/ruby/network/simple/SimpleNetwork.hh +++ b/src/mem/ruby/network/simple/SimpleNetwork.hh @@ -93,7 +93,8 @@ class SimpleNetwork : public Network SimpleNetwork& operator=(const SimpleNetwork& obj); std::vector<Switch*> m_switches; - std::vector<MessageBuffer*> m_buffers_to_free; + std::vector<MessageBuffer*> m_int_link_buffers; + int m_num_connected_buffers; std::vector<Switch*> m_endpoint_switches; int m_buffer_size; diff --git a/src/mem/ruby/network/simple/SimpleNetwork.py b/src/mem/ruby/network/simple/SimpleNetwork.py index 8d0442b7d..f4ec440a3 100644 --- a/src/mem/ruby/network/simple/SimpleNetwork.py +++ b/src/mem/ruby/network/simple/SimpleNetwork.py @@ -31,6 +31,7 @@ from m5.params import * from m5.proxy import * from Network import RubyNetwork from BasicRouter import BasicRouter +from MessageBuffer import MessageBuffer class SimpleNetwork(RubyNetwork): type = 'SimpleNetwork' @@ -39,9 +40,48 @@ class SimpleNetwork(RubyNetwork): "default buffer size; 0 indicates infinite buffering"); endpoint_bandwidth = Param.Int(1000, "bandwidth adjustment factor"); adaptive_routing = Param.Bool(False, "enable adaptive routing"); + int_link_buffers = VectorParam.MessageBuffer("Buffers for int_links") + # int_links do not recycle buffers, so this parameter is not used. + # TODO: Move recycle_latency out of MessageBuffers and into controllers + recycle_latency = Param.Cycles(0, "") + + def setup_buffers(self): + # Note that all SimpleNetwork MessageBuffers are currently ordered + network_buffers = [] + for link in self.int_links: + # The network needs number_of_virtual_networks buffers per + # int_link port + for i in xrange(self.number_of_virtual_networks): + network_buffers.append(MessageBuffer(ordered = True)) + network_buffers.append(MessageBuffer(ordered = True)) + self.int_link_buffers = network_buffers + + # Also add buffers for all router-link connections + for router in self.routers: + router_buffers = [] + # Add message buffers to routers for each internal link connection + for link in self.int_links: + if link.node_a == router: + for i in xrange(self.number_of_virtual_networks): + router_buffers.append(MessageBuffer(ordered = True)) + if link.node_b == router: + for i in xrange(self.number_of_virtual_networks): + router_buffers.append(MessageBuffer(ordered = True)) + + # Add message buffers to routers for each external link connection + for link in self.ext_links: + # Routers can only be int_nodes on ext_links + if link.int_node in self.routers: + for i in xrange(self.number_of_virtual_networks): + router_buffers.append(MessageBuffer(ordered = True)) + router.port_buffers = router_buffers class Switch(BasicRouter): type = 'Switch' cxx_header = 'mem/ruby/network/simple/Switch.hh' virt_nets = Param.Int(Parent.number_of_virtual_networks, "number of virtual networks") + port_buffers = VectorParam.MessageBuffer("Port buffers") + # Ports do not recycle buffers, so this parameter is not used. + # TODO: Move recycle_latency out of MessageBuffers and into controllers + recycle_latency = Param.Cycles(0, "") diff --git a/src/mem/ruby/network/simple/Switch.cc b/src/mem/ruby/network/simple/Switch.cc index 431a7b28f..b9d0b8010 100644 --- a/src/mem/ruby/network/simple/Switch.cc +++ b/src/mem/ruby/network/simple/Switch.cc @@ -43,6 +43,8 @@ using m5::stl_helpers::operator<<; Switch::Switch(const Params *p) : BasicRouter(p) { m_perfect_switch = new PerfectSwitch(m_id, this, p->virt_nets); + m_port_buffers = p->port_buffers; + m_num_connected_buffers = 0; } Switch::~Switch() @@ -53,7 +55,7 @@ Switch::~Switch() deletePointers(m_throttles); // Delete MessageBuffers - deletePointers(m_buffers_to_free); + deletePointers(m_port_buffers); } void @@ -97,15 +99,10 @@ Switch::addOutPort(const vector<MessageBuffer*>& out, out[i]->setSender(this); } - MessageBuffer* buffer_ptr = new MessageBuffer; - // Make these queues ordered - buffer_ptr->setOrdering(true); - if (m_network_ptr->getBufferSize() > 0) { - buffer_ptr->resize(m_network_ptr->getBufferSize()); - } - + assert(m_num_connected_buffers < m_port_buffers.size()); + MessageBuffer* buffer_ptr = m_port_buffers[m_num_connected_buffers]; + m_num_connected_buffers++; intermediateBuffers.push_back(buffer_ptr); - m_buffers_to_free.push_back(buffer_ptr); buffer_ptr->setSender(this); buffer_ptr->setReceiver(this); @@ -188,8 +185,8 @@ bool Switch::functionalRead(Packet *pkt) { // Access the buffers in the switch for performing a functional read - for (unsigned int i = 0; i < m_buffers_to_free.size(); ++i) { - if (m_buffers_to_free[i]->functionalRead(pkt)) { + for (unsigned int i = 0; i < m_port_buffers.size(); ++i) { + if (m_port_buffers[i]->functionalRead(pkt)) { return true; } } @@ -201,8 +198,8 @@ Switch::functionalWrite(Packet *pkt) { // Access the buffers in the switch for performing a functional write uint32_t num_functional_writes = 0; - for (unsigned int i = 0; i < m_buffers_to_free.size(); ++i) { - num_functional_writes += m_buffers_to_free[i]->functionalWrite(pkt); + for (unsigned int i = 0; i < m_port_buffers.size(); ++i) { + num_functional_writes += m_port_buffers[i]->functionalWrite(pkt); } return num_functional_writes; } diff --git a/src/mem/ruby/network/simple/Switch.hh b/src/mem/ruby/network/simple/Switch.hh index 3c11a5fa0..dbb1bbd05 100644 --- a/src/mem/ruby/network/simple/Switch.hh +++ b/src/mem/ruby/network/simple/Switch.hh @@ -89,7 +89,8 @@ class Switch : public BasicRouter PerfectSwitch* m_perfect_switch; SimpleNetwork* m_network_ptr; std::vector<Throttle*> m_throttles; - std::vector<MessageBuffer*> m_buffers_to_free; + std::vector<MessageBuffer*> m_port_buffers; + unsigned m_num_connected_buffers; // Statistical variables Stats::Formula m_avg_utilization; diff --git a/src/mem/ruby/network/simple/Throttle.cc b/src/mem/ruby/network/simple/Throttle.cc index 2164d76de..785e09aa2 100644 --- a/src/mem/ruby/network/simple/Throttle.cc +++ b/src/mem/ruby/network/simple/Throttle.cc @@ -100,7 +100,6 @@ Throttle::addLinks(const vector<MessageBuffer*>& in_vec, in_ptr->setConsumer(this); string desc = "[Queue to Throttle " + to_string(m_sID) + " " + to_string(m_node) + "]"; - in_ptr->setDescription(desc); } } |