diff options
Diffstat (limited to 'src/mem/ruby/network/simple')
39 files changed, 6118 insertions, 0 deletions
diff --git a/src/mem/ruby/network/simple/Network_Files/GarnetFileMaker.py b/src/mem/ruby/network/simple/Network_Files/GarnetFileMaker.py new file mode 100644 index 000000000..b47bb0161 --- /dev/null +++ b/src/mem/ruby/network/simple/Network_Files/GarnetFileMaker.py @@ -0,0 +1,45 @@ +#!/s/std/bin/python +import sys, os, string, re, math + +rows = 0 +cols =0 + +if len(sys.argv) == 3: + rows = int(sys.argv[1]) + cols = int(sys.argv[2]) +else: + sys.stderr.write("usage : GarnetFileMaker.py <rows> <cols> \n\n") + +banks = rows*cols +bank = 0 +while bank < banks: + sys.stdout.write("ext_node:L1Cache:%d int_node:%d link_latency:1 \n" % (bank, bank)) + sys.stdout.write("ext_node:L2Cache:%d int_node:%d link_latency:1 \n" % (bank, bank)) + bank += 1 + +sys.stdout.write("\n") + +col = 0 +while col < cols: + row = 1 + bank = col*rows + while row < rows: + sys.stdout.write("int_node:%d int_node:%d link_latency:1 link_weight:1\n" % (bank, bank+1)) + bank += 1 + row += 1 + sys.stdout.write("\n") + col += 1 + +sys.stdout.write("\n") + +row = 0 +while row < rows: + col = 1 + bank = row + while col < cols: + sys.stdout.write("int_node:%d int_node:%d link_latency:1 link_weight:2\n" % (bank, rows+bank)) + bank += rows + col += 1 + sys.stdout.write("\n") + row += 1 + diff --git a/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt b/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt new file mode 100644 index 000000000..1304a5e0a --- /dev/null +++ b/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt @@ -0,0 +1,78 @@ + +processors:16 +procs_per_chip:16 +L2banks:16 +memories:16 + +ext_node:L1Cache:0 int_node:0 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:1 int_node:1 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:2 int_node:2 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:3 int_node:3 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:4 int_node:4 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:5 int_node:5 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:6 int_node:6 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:7 int_node:7 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:8 int_node:8 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:9 int_node:9 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:10 int_node:10 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:11 int_node:11 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:12 int_node:12 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:13 int_node:13 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:14 int_node:14 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:15 int_node:15 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:0 int_node:0 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:1 int_node:1 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:2 int_node:2 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:3 int_node:3 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:4 int_node:4 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:5 int_node:5 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:6 int_node:6 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:7 int_node:7 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:8 int_node:8 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:9 int_node:9 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:10 int_node:10 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:11 int_node:11 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:12 int_node:12 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:13 int_node:13 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:14 int_node:14 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:15 int_node:15 link_latency:1 bw_multiplier:72 +ext_node:Directory:0 int_node:0 link_latency:20 bw_multiplier:80 +ext_node:Directory:1 int_node:1 link_latency:20 bw_multiplier:80 +ext_node:Directory:2 int_node:2 link_latency:20 bw_multiplier:80 +ext_node:Directory:3 int_node:3 link_latency:20 bw_multiplier:80 +ext_node:Directory:4 int_node:4 link_latency:20 bw_multiplier:80 +ext_node:Directory:5 int_node:5 link_latency:20 bw_multiplier:80 +ext_node:Directory:6 int_node:6 link_latency:20 bw_multiplier:80 +ext_node:Directory:7 int_node:7 link_latency:20 bw_multiplier:80 +ext_node:Directory:8 int_node:8 link_latency:20 bw_multiplier:80 +ext_node:Directory:9 int_node:9 link_latency:20 bw_multiplier:80 +ext_node:Directory:10 int_node:10 link_latency:20 bw_multiplier:80 +ext_node:Directory:11 int_node:11 link_latency:20 bw_multiplier:80 +ext_node:Directory:12 int_node:12 link_latency:20 bw_multiplier:80 +ext_node:Directory:13 int_node:13 link_latency:20 bw_multiplier:80 +ext_node:Directory:14 int_node:14 link_latency:20 bw_multiplier:80 +ext_node:Directory:15 int_node:15 link_latency:20 bw_multiplier:80 +int_node:0 int_node:1 link_latency:1 bw_multiplier:72 +int_node:1 int_node:2 link_latency:1 bw_multiplier:72 +int_node:2 int_node:3 link_latency:1 bw_multiplier:72 +int_node:0 int_node:4 link_latency:1 bw_multiplier:72 link_weight:2 +int_node:1 int_node:5 link_latency:1 bw_multiplier:72 link_weight:2 +int_node:2 int_node:6 link_latency:1 bw_multiplier:72 link_weight:2 +int_node:3 int_node:7 link_latency:1 bw_multiplier:72 link_weight:2 +int_node:4 int_node:5 link_latency:1 bw_multiplier:72 +int_node:5 int_node:6 link_latency:1 bw_multiplier:72 +int_node:6 int_node:7 link_latency:1 bw_multiplier:72 +int_node:4 int_node:8 link_latency:1 bw_multiplier:72 link_weight:2 +int_node:5 int_node:9 link_latency:1 bw_multiplier:72 link_weight:2 +int_node:6 int_node:10 link_latency:1 bw_multiplier:72 link_weight:2 +int_node:7 int_node:11 link_latency:1 bw_multiplier:72 link_weight:2 +int_node:8 int_node:9 link_latency:1 bw_multiplier:72 +int_node:9 int_node:10 link_latency:1 bw_multiplier:72 +int_node:10 int_node:11 link_latency:1 bw_multiplier:72 +int_node:8 int_node:12 link_latency:1 bw_multiplier:72 link_weight:2 +int_node:9 int_node:13 link_latency:1 bw_multiplier:72 link_weight:2 +int_node:10 int_node:14 link_latency:1 bw_multiplier:72 link_weight:2 +int_node:11 int_node:15 link_latency:1 bw_multiplier:72 link_weight:2 +int_node:12 int_node:13 link_latency:1 bw_multiplier:72 +int_node:13 int_node:14 link_latency:1 bw_multiplier:72 +int_node:14 int_node:15 link_latency:1 bw_multiplier:72 diff --git a/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-4.txt b/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-4.txt new file mode 100644 index 000000000..329156a33 --- /dev/null +++ b/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-4.txt @@ -0,0 +1,56 @@ + +processors:16 +procs_per_chip:16 +L2banks:16 +memories:4 + +ext_node:L1Cache:0 int_node:0 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:1 int_node:0 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:2 int_node:1 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:3 int_node:1 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:4 int_node:2 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:5 int_node:2 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:6 int_node:3 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:7 int_node:3 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:8 int_node:4 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:9 int_node:4 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:10 int_node:5 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:11 int_node:5 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:12 int_node:6 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:13 int_node:6 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:14 int_node:7 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:15 int_node:7 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:0 int_node:0 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:1 int_node:0 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:2 int_node:1 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:3 int_node:1 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:4 int_node:2 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:5 int_node:2 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:6 int_node:3 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:7 int_node:3 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:8 int_node:4 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:9 int_node:4 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:10 int_node:5 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:11 int_node:5 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:12 int_node:6 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:13 int_node:6 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:14 int_node:7 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:15 int_node:7 link_latency:1 bw_multiplier:72 +int_node:11 int_node:12 link_latency:1 bw_multiplier:72 +int_node:8 int_node:13 link_latency:1 bw_multiplier:72 +int_node:0 int_node:8 link_latency:1 bw_multiplier:72 +int_node:4 int_node:8 link_latency:1 bw_multiplier:72 +int_node:1 int_node:9 link_latency:1 bw_multiplier:72 +int_node:5 int_node:9 link_latency:1 bw_multiplier:72 +int_node:2 int_node:10 link_latency:1 bw_multiplier:72 +int_node:6 int_node:10 link_latency:1 bw_multiplier:72 +int_node:3 int_node:11 link_latency:1 bw_multiplier:72 +int_node:7 int_node:11 link_latency:1 bw_multiplier:72 +int_node:8 int_node:9 link_latency:1 bw_multiplier:72 +int_node:9 int_node:10 link_latency:1 bw_multiplier:72 +int_node:10 int_node:11 link_latency:1 bw_multiplier:72 +ext_node:Directory:0 int_node:12 link_latency:20 bw_multiplier:80 +ext_node:Directory:1 int_node:12 link_latency:20 bw_multiplier:80 +ext_node:Directory:2 int_node:13 link_latency:20 bw_multiplier:80 +ext_node:Directory:3 int_node:13 link_latency:20 bw_multiplier:80 + diff --git a/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-8.txt b/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-8.txt new file mode 100644 index 000000000..7b714cdc1 --- /dev/null +++ b/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-8.txt @@ -0,0 +1,61 @@ + +processors:16 +procs_per_chip:16 +L2banks:16 +memories:8 + +ext_node:L1Cache:0 int_node:0 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:1 int_node:0 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:2 int_node:1 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:3 int_node:1 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:4 int_node:2 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:5 int_node:2 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:6 int_node:3 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:7 int_node:3 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:8 int_node:4 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:9 int_node:4 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:10 int_node:5 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:11 int_node:5 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:12 int_node:6 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:13 int_node:6 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:14 int_node:7 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:15 int_node:7 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:0 int_node:0 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:1 int_node:0 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:2 int_node:1 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:3 int_node:1 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:4 int_node:2 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:5 int_node:2 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:6 int_node:3 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:7 int_node:3 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:8 int_node:4 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:9 int_node:4 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:10 int_node:5 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:11 int_node:5 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:12 int_node:6 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:13 int_node:6 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:14 int_node:7 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:15 int_node:7 link_latency:1 bw_multiplier:72 +int_node:12 int_node:13 link_latency:20 bw_multiplier:10 +int_node:9 int_node:12 link_latency:1 bw_multiplier:72 +int_node:10 int_node:12 link_latency:1 bw_multiplier:72 +int_node:0 int_node:8 link_latency:1 bw_multiplier:72 +int_node:4 int_node:8 link_latency:1 bw_multiplier:72 +int_node:1 int_node:9 link_latency:1 bw_multiplier:72 +int_node:5 int_node:9 link_latency:1 bw_multiplier:72 +int_node:2 int_node:10 link_latency:1 bw_multiplier:72 +int_node:6 int_node:10 link_latency:1 bw_multiplier:72 +int_node:3 int_node:11 link_latency:1 bw_multiplier:72 +int_node:7 int_node:11 link_latency:1 bw_multiplier:72 +int_node:8 int_node:9 link_latency:1 bw_multiplier:72 +int_node:9 int_node:10 link_latency:1 bw_multiplier:72 +int_node:10 int_node:11 link_latency:1 bw_multiplier:72 +ext_node:Directory:0 int_node:13 link_latency:20 bw_multiplier:80 +ext_node:Directory:1 int_node:13 link_latency:20 bw_multiplier:80 +ext_node:Directory:2 int_node:13 link_latency:20 bw_multiplier:80 +ext_node:Directory:3 int_node:13 link_latency:20 bw_multiplier:80 +ext_node:Directory:4 int_node:13 link_latency:20 bw_multiplier:80 +ext_node:Directory:5 int_node:13 link_latency:20 bw_multiplier:80 +ext_node:Directory:6 int_node:13 link_latency:20 bw_multiplier:80 +ext_node:Directory:7 int_node:13 link_latency:20 bw_multiplier:80 + diff --git a/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-1_L2Banks-16_Memories-16.txt b/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-1_L2Banks-16_Memories-16.txt new file mode 100644 index 000000000..b1a262d42 --- /dev/null +++ b/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-1_L2Banks-16_Memories-16.txt @@ -0,0 +1,190 @@ + +processors:16 +procs_per_chip:1 +L2banks:16 +memories:16 +bw_unit:1000 + +ext_node:L1Cache:0 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L2Cache:0 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:Directory:0 int_node:0 link_latency:40 bw_multiplier:10 +int_node:0 int_node:1 link_latency:40 bw_multiplier:16 +int_node:0 int_node:2 link_latency:40 bw_multiplier:16 +int_node:0 int_node:3 link_latency:40 bw_multiplier:16 +int_node:0 int_node:4 link_latency:40 bw_multiplier:16 +int_node:0 int_node:5 link_latency:40 bw_multiplier:16 +int_node:0 int_node:6 link_latency:40 bw_multiplier:16 +int_node:0 int_node:7 link_latency:40 bw_multiplier:16 +int_node:0 int_node:8 link_latency:40 bw_multiplier:16 +int_node:0 int_node:9 link_latency:40 bw_multiplier:16 +int_node:0 int_node:10 link_latency:40 bw_multiplier:16 +int_node:0 int_node:11 link_latency:40 bw_multiplier:16 +int_node:0 int_node:12 link_latency:40 bw_multiplier:16 +int_node:0 int_node:13 link_latency:40 bw_multiplier:16 +int_node:0 int_node:14 link_latency:40 bw_multiplier:16 +int_node:0 int_node:15 link_latency:40 bw_multiplier:16 + +ext_node:L1Cache:1 int_node:1 link_latency:1 bw_multiplier:64 +ext_node:L2Cache:1 int_node:1 link_latency:1 bw_multiplier:64 +ext_node:Directory:1 int_node:1 link_latency:40 bw_multiplier:10 +int_node:1 int_node:2 link_latency:40 bw_multiplier:16 +int_node:1 int_node:3 link_latency:40 bw_multiplier:16 +int_node:1 int_node:4 link_latency:40 bw_multiplier:16 +int_node:1 int_node:5 link_latency:40 bw_multiplier:16 +int_node:1 int_node:6 link_latency:40 bw_multiplier:16 +int_node:1 int_node:7 link_latency:40 bw_multiplier:16 +int_node:1 int_node:8 link_latency:40 bw_multiplier:16 +int_node:1 int_node:9 link_latency:40 bw_multiplier:16 +int_node:1 int_node:10 link_latency:40 bw_multiplier:16 +int_node:1 int_node:11 link_latency:40 bw_multiplier:16 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link_latency:1 bw_multiplier:16 +int_node:37 int_node:39 link_latency:1 bw_multiplier:16 +int_node:38 int_node:39 link_latency:1 bw_multiplier:16 + + diff --git a/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-16.txt b/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-16.txt new file mode 100644 index 000000000..fc1cef27a --- /dev/null +++ b/src/mem/ruby/network/simple/Network_Files/NUCA_Procs-16_ProcsPerChip-4_L2Banks-4_Memories-16.txt @@ -0,0 +1,78 @@ + +processors:16 +procs_per_chip:4 +L2banks:4 +memories:16 +bw_unit:1000 + +ext_node:L1Cache:0 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L1Cache:1 int_node:1 link_latency:1 bw_multiplier:64 +ext_node:L1Cache:2 int_node:2 link_latency:1 bw_multiplier:64 +ext_node:L1Cache:3 int_node:3 link_latency:1 bw_multiplier:64 +ext_node:L2Cache:0 int_node:5 link_latency:1 bw_multiplier:64 +ext_node:Directory:0 int_node:6 link_latency:20 bw_multiplier:10 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link_latency:1 bw_multiplier:72 + +int_node:6 int_node:7 link_latency:20 bw_multiplier:10 + +ext_node:Directory:0 int_node:7 link_latency:20 bw_multiplier:80 +ext_node:Directory:1 int_node:7 link_latency:20 bw_multiplier:80 +ext_node:Directory:2 int_node:7 link_latency:20 bw_multiplier:80 +ext_node:Directory:3 int_node:7 link_latency:20 bw_multiplier:80 +ext_node:Directory:4 int_node:7 link_latency:20 bw_multiplier:80 +ext_node:Directory:5 int_node:7 link_latency:20 bw_multiplier:80 +ext_node:Directory:6 int_node:7 link_latency:20 bw_multiplier:80 +ext_node:Directory:7 int_node:7 link_latency:20 bw_multiplier:80 + diff --git a/src/mem/ruby/network/simple/Network_Files/NetworkFileMaker.py b/src/mem/ruby/network/simple/Network_Files/NetworkFileMaker.py new file mode 100644 index 000000000..7d07588a1 --- /dev/null +++ b/src/mem/ruby/network/simple/Network_Files/NetworkFileMaker.py @@ -0,0 +1,44 @@ +#!/s/std/bin/python +import sys, os, string, re, math + +rows = 0 +cols =0 + +if len(sys.argv) == 3: + rows = int(sys.argv[1]) + cols = int(sys.argv[2]) +else: + sys.stderr.write("usage : NetworkFileMaker.py <rows> <cols> \n\n") + +banks = rows*cols +bank = 0 +while bank < banks: + sys.stdout.write("ext_node:L2Cache:0:bank:%d int_node:%d link_latency:1 bw_multiplier:16\n" % (bank, bank)) + bank += 1 + +sys.stdout.write("\n") + +col = 0 +while col < cols: + row = 1 + bank = col*rows + while row < rows: + sys.stdout.write("int_node:%d int_node:%d link_latency:1 bw_multiplier:16\n" % (bank, bank+1)) + bank += 1 + row += 1 + sys.stdout.write("\n") + col += 1 + +sys.stdout.write("\n") + +row = 0 +while row < rows: + col = 1 + bank = row + while col < cols: + sys.stdout.write("int_node:%d int_node:%d link_latency:1 bw_multiplier:16\n" % (bank, rows+bank)) + bank += rows + col += 1 + sys.stdout.write("\n") + row += 1 + diff --git a/src/mem/ruby/network/simple/Network_Files/TLC_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt b/src/mem/ruby/network/simple/Network_Files/TLC_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt new file mode 100644 index 000000000..d43386237 --- /dev/null +++ b/src/mem/ruby/network/simple/Network_Files/TLC_Procs-8_ProcsPerChip-8_L2Banks-256_Memories-8.txt @@ -0,0 +1,367 @@ + +processors:8 +procs_per_chip:8 +L2banks:256 +memories:8 + +ext_node:L1Cache:0 int_node:0 link_weight:1 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:1 int_node:2 link_weight:1 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:2 int_node:2 link_weight:1 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:3 int_node:4 link_weight:1 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:4 int_node:0 link_weight:1 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:5 int_node:2 link_weight:1 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:6 int_node:2 link_weight:1 link_latency:1 bw_multiplier:72 +ext_node:L1Cache:7 int_node:4 link_weight:1 link_latency:1 bw_multiplier:72 +ext_node:L2Cache:0 int_node:22 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link_latency:1 bw_multiplier:8 +int_node:4 int_node:20 link_weight:1 link_latency:1 bw_multiplier:8 + diff --git a/src/mem/ruby/network/simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt b/src/mem/ruby/network/simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt new file mode 100644 index 000000000..b6b1dbd98 --- /dev/null +++ b/src/mem/ruby/network/simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-16_L2Banks-16_Memories-16.txt @@ -0,0 +1,74 @@ + +processors:16 +procs_per_chip:16 +L2banks:16 +memories:16 +bw_unit:10000 + +ext_node:L1Cache:0 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L1Cache:1 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L1Cache:2 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L1Cache:3 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L1Cache:4 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L1Cache:5 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L1Cache:6 int_node:0 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bw_multiplier:10 + diff --git a/src/mem/ruby/network/simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt b/src/mem/ruby/network/simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt new file mode 100644 index 000000000..28a9be8f5 --- /dev/null +++ b/src/mem/ruby/network/simple/Network_Files/TOKEN_CMP_Procs-16_ProcsPerChip-4_L2Banks-16_Memories-16.txt @@ -0,0 +1,101 @@ + +processors:16 +procs_per_chip:4 +L2banks:16 +memories:16 +bw_unit:1000 + +ext_node:L1Cache:0 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L1Cache:1 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L1Cache:2 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L1Cache:3 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L2Cache:0 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L2Cache:1 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L2Cache:2 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:L2Cache:3 int_node:0 link_latency:1 bw_multiplier:64 +ext_node:Directory:0 int_node:2 link_latency:20 bw_multiplier:10 +ext_node:Directory:1 int_node:2 link_latency:20 bw_multiplier:10 +ext_node:Directory:2 int_node:2 link_latency:20 bw_multiplier:10 +ext_node:Directory:3 int_node:2 link_latency:20 bw_multiplier:10 +ext_node:PersistentArbiter:0 int_node:2 link_latency:20 bw_multiplier:10 +ext_node:PersistentArbiter:1 int_node:2 link_latency:20 bw_multiplier:10 +ext_node:PersistentArbiter:2 int_node:2 link_latency:20 bw_multiplier:10 +ext_node:PersistentArbiter:3 int_node:2 link_latency:20 bw_multiplier:10 +int_node:0 int_node:1 link_latency:1 bw_multiplier:16 +int_node:1 int_node:2 link_latency:20 bw_multiplier:10 +int_node:0 int_node:16 link_latency:1 bw_multiplier:16 +int_node:16 int_node:3 link_latency:1 bw_multiplier:16 + +int_node:3 int_node:7 link_latency:20 bw_multiplier:10 + +ext_node:L1Cache:4 int_node:4 link_latency:1 bw_multiplier:64 +ext_node:L1Cache:5 int_node:4 link_latency:1 bw_multiplier:64 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+int_node:15 int_node:7 link_latency:20 bw_multiplier:10 +int_node:11 int_node:3 link_latency:20 bw_multiplier:10 + diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc b/src/mem/ruby/network/simple/PerfectSwitch.cc new file mode 100644 index 000000000..a88a29e83 --- /dev/null +++ b/src/mem/ruby/network/simple/PerfectSwitch.cc @@ -0,0 +1,319 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * PerfectSwitch.C + * + * Description: See PerfectSwitch.h + * + * $Id$ + * + */ + + +#include "PerfectSwitch.hh" +#include "NetworkMessage.hh" +#include "Profiler.hh" +#include "System.hh" +#include "SimpleNetwork.hh" +#include "util.hh" +#include "MessageBuffer.hh" +#include "Protocol.hh" + +const int PRIORITY_SWITCH_LIMIT = 128; + +// Operator for helper class +bool operator<(const LinkOrder& l1, const LinkOrder& l2) { + return (l1.m_value < l2.m_value); +} + +PerfectSwitch::PerfectSwitch(SwitchID sid, SimpleNetwork* network_ptr) +{ + m_virtual_networks = NUMBER_OF_VIRTUAL_NETWORKS; // FIXME - pass me as a parameter? + m_switch_id = sid; + m_round_robin_start = 0; + m_network_ptr = network_ptr; + m_wakeups_wo_switch = 0; +} + +void PerfectSwitch::addInPort(const Vector<MessageBuffer*>& in) +{ + assert(in.size() == m_virtual_networks); + NodeID port = m_in.size(); + m_in.insertAtBottom(in); + for (int j = 0; j < m_virtual_networks; j++) { + m_in[port][j]->setConsumer(this); + string desc = "[Queue from port " + NodeIDToString(m_switch_id) + " " + NodeIDToString(port) + " " + NodeIDToString(j) + " to PerfectSwitch]"; + m_in[port][j]->setDescription(desc); + } +} + +void PerfectSwitch::addOutPort(const Vector<MessageBuffer*>& out, const NetDest& routing_table_entry) +{ + assert(out.size() == m_virtual_networks); + + // Setup link order + LinkOrder l; + l.m_value = 0; + l.m_link = m_out.size(); + m_link_order.insertAtBottom(l); + + // Add to routing table + m_out.insertAtBottom(out); + m_routing_table.insertAtBottom(routing_table_entry); + + if (g_PRINT_TOPOLOGY) { + m_out_link_vec.insertAtBottom(out); + } +} + +void PerfectSwitch::clearRoutingTables() +{ + m_routing_table.clear(); +} + +void PerfectSwitch::clearBuffers() +{ + for(int i=0; i<m_in.size(); i++){ + for(int vnet=0; vnet < m_virtual_networks; vnet++) { + m_in[i][vnet]->clear(); + } + } + + for(int i=0; i<m_out.size(); i++){ + for(int vnet=0; vnet < m_virtual_networks; vnet++) { + m_out[i][vnet]->clear(); + } + } +} + +void PerfectSwitch::reconfigureOutPort(const NetDest& routing_table_entry) +{ + m_routing_table.insertAtBottom(routing_table_entry); +} + +PerfectSwitch::~PerfectSwitch() +{ +} + +void PerfectSwitch::wakeup() +{ + + DEBUG_EXPR(NETWORK_COMP, MedPrio, m_switch_id); + + MsgPtr msg_ptr; + + // Give the highest numbered link priority most of the time + m_wakeups_wo_switch++; + int highest_prio_vnet = m_virtual_networks-1; + int lowest_prio_vnet = 0; + int decrementer = 1; + bool schedule_wakeup = false; + NetworkMessage* net_msg_ptr = NULL; + + // invert priorities to avoid starvation seen in the component network + if (m_wakeups_wo_switch > PRIORITY_SWITCH_LIMIT) { + m_wakeups_wo_switch = 0; + highest_prio_vnet = 0; + lowest_prio_vnet = m_virtual_networks-1; + decrementer = -1; + } + + for (int vnet = highest_prio_vnet; (vnet*decrementer) >= (decrementer*lowest_prio_vnet); vnet -= decrementer) { + + // For all components incoming queues + int incoming = m_round_robin_start; // This is for round-robin scheduling + m_round_robin_start++; + if (m_round_robin_start >= m_in.size()) { + m_round_robin_start = 0; + } + + // for all input ports, use round robin scheduling + for (int counter = 0; counter < m_in.size(); counter++) { + + // Round robin scheduling + incoming++; + if (incoming >= m_in.size()) { + incoming = 0; + } + + // temporary vectors to store the routing results + Vector<LinkID> output_links; + Vector<NetDest> output_link_destinations; + + // Is there a message waiting? + while (m_in[incoming][vnet]->isReady()) { + + DEBUG_EXPR(NETWORK_COMP, MedPrio, incoming); + + // Peek at message + msg_ptr = m_in[incoming][vnet]->peekMsgPtr(); + net_msg_ptr = dynamic_cast<NetworkMessage*>(msg_ptr.ref()); + DEBUG_EXPR(NETWORK_COMP, MedPrio, *net_msg_ptr); + + output_links.clear(); + output_link_destinations.clear(); + NetDest msg_destinations = net_msg_ptr->getInternalDestination(); + + // Unfortunately, the token-protocol sends some + // zero-destination messages, so this assert isn't valid + // assert(msg_destinations.count() > 0); + + assert(m_link_order.size() == m_routing_table.size()); + assert(m_link_order.size() == m_out.size()); + + if (g_adaptive_routing) { + if (m_network_ptr->isVNetOrdered(vnet)) { + // Don't adaptively route + for (int outlink=0; outlink<m_out.size(); outlink++) { + m_link_order[outlink].m_link = outlink; + m_link_order[outlink].m_value = 0; + } + } else { + // Find how clogged each link is + for (int outlink=0; outlink<m_out.size(); outlink++) { + int out_queue_length = 0; + for (int v=0; v<m_virtual_networks; v++) { + out_queue_length += m_out[outlink][v]->getSize(); + } + m_link_order[outlink].m_link = outlink; + m_link_order[outlink].m_value = 0; + m_link_order[outlink].m_value |= (out_queue_length << 8); + m_link_order[outlink].m_value |= (random() & 0xff); + } + m_link_order.sortVector(); // Look at the most empty link first + } + } + + for (int i=0; i<m_routing_table.size(); i++) { + // pick the next link to look at + int link = m_link_order[i].m_link; + + DEBUG_EXPR(NETWORK_COMP, MedPrio, m_routing_table[link]); + + if (msg_destinations.intersectionIsNotEmpty(m_routing_table[link])) { + + // Remember what link we're using + output_links.insertAtBottom(link); + + // Need to remember which destinations need this message + // in another vector. This Set is the intersection of the + // routing_table entry and the current destination set. + // The intersection must not be empty, since we are inside "if" + output_link_destinations.insertAtBottom(msg_destinations.AND(m_routing_table[link])); + + // Next, we update the msg_destination not to include + // those nodes that were already handled by this link + msg_destinations.removeNetDest(m_routing_table[link]); + } + } + + assert(msg_destinations.count() == 0); + //assert(output_links.size() > 0); + + // Check for resources - for all outgoing queues + bool enough = true; + for (int i=0; i<output_links.size(); i++) { + int outgoing = output_links[i]; + enough = enough && m_out[outgoing][vnet]->areNSlotsAvailable(1); + DEBUG_MSG(NETWORK_COMP, HighPrio, "checking if node is blocked"); + DEBUG_EXPR(NETWORK_COMP, HighPrio, outgoing); + DEBUG_EXPR(NETWORK_COMP, HighPrio, vnet); + DEBUG_EXPR(NETWORK_COMP, HighPrio, enough); + } + + // There were not enough resources + if(!enough) { + g_eventQueue_ptr->scheduleEvent(this, 1); + DEBUG_MSG(NETWORK_COMP, HighPrio, "Can't deliver message to anyone since a node is blocked"); + DEBUG_EXPR(NETWORK_COMP, HighPrio, *net_msg_ptr); + break; // go to next incoming port + } + + MsgPtr unmodified_msg_ptr; + + if (output_links.size() > 1) { + // If we are sending this message down more than one link + // (size>1), we need to make a copy of the message so each + // branch can have a different internal destination + // we need to create an unmodified MsgPtr because the MessageBuffer enqueue func + // will modify the message + unmodified_msg_ptr = *(msg_ptr.ref()); // This magic line creates a private copy of the message + } + + // Enqueue it - for all outgoing queues + for (int i=0; i<output_links.size(); i++) { + int outgoing = output_links[i]; + + if (i > 0) { + msg_ptr = *(unmodified_msg_ptr.ref()); // create a private copy of the unmodified message + } + + // Change the internal destination set of the message so it + // knows which destinations this link is responsible for. + net_msg_ptr = dynamic_cast<NetworkMessage*>(msg_ptr.ref()); + net_msg_ptr->getInternalDestination() = output_link_destinations[i]; + + // Enqeue msg + DEBUG_NEWLINE(NETWORK_COMP,HighPrio); + DEBUG_MSG(NETWORK_COMP,HighPrio,"switch: " + int_to_string(m_switch_id) + + " enqueuing net msg from inport[" + int_to_string(incoming) + "][" + + int_to_string(vnet) +"] to outport [" + int_to_string(outgoing) + + "][" + int_to_string(vnet) +"]" + + " time: " + int_to_string(g_eventQueue_ptr->getTime()) + "."); + DEBUG_NEWLINE(NETWORK_COMP,HighPrio); + + m_out[outgoing][vnet]->enqueue(msg_ptr); + } + + // Dequeue msg + m_in[incoming][vnet]->pop(); + } + } + } +} + +void PerfectSwitch::printStats(ostream& out) const +{ + out << "PerfectSwitch printStats" << endl; +} + +void PerfectSwitch::clearStats() +{ +} + +void PerfectSwitch::printConfig(ostream& out) const +{ +} + +void PerfectSwitch::print(ostream& out) const +{ + out << "[PerfectSwitch " << m_switch_id << "]"; +} + diff --git a/src/mem/ruby/network/simple/PerfectSwitch.hh b/src/mem/ruby/network/simple/PerfectSwitch.hh new file mode 100644 index 000000000..4d381ccc9 --- /dev/null +++ b/src/mem/ruby/network/simple/PerfectSwitch.hh @@ -0,0 +1,118 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $Id$ + * + * Description: Perfect switch, of course it is perfect and no latency or what + * so ever. Every cycle it is woke up and perform all the + * necessary routings that must be done. Note, this switch also + * has number of input ports/output ports and has a routing table + * as well. + * + */ + +#ifndef PerfectSwitch_H +#define PerfectSwitch_H + +#include "Global.hh" +#include "Vector.hh" +#include "Consumer.hh" +#include "NodeID.hh" + +class MessageBuffer; +class NetDest; +class SimpleNetwork; + +class LinkOrder { +public: + int m_link; + int m_value; +}; + +class PerfectSwitch : public Consumer { +public: + // Constructors + + // constructor specifying the number of ports + PerfectSwitch(SwitchID sid, SimpleNetwork* network_ptr); + void addInPort(const Vector<MessageBuffer*>& in); + void addOutPort(const Vector<MessageBuffer*>& out, const NetDest& routing_table_entry); + void clearRoutingTables(); + void clearBuffers(); + void reconfigureOutPort(const NetDest& routing_table_entry); + int getInLinks() const { return m_in.size(); } + int getOutLinks() const { return m_out.size(); } + + // Destructor + ~PerfectSwitch(); + + // Public Methods + void wakeup(); + + void printStats(ostream& out) const; + void clearStats(); + void printConfig(ostream& out) const; + + void print(ostream& out) const; +private: + + // Private copy constructor and assignment operator + PerfectSwitch(const PerfectSwitch& obj); + PerfectSwitch& operator=(const PerfectSwitch& obj); + + // Data Members (m_ prefix) + SwitchID m_switch_id; + + // vector of queues from the components + Vector<Vector<MessageBuffer*> > m_in; + Vector<Vector<MessageBuffer*> > m_out; + Vector<NetDest> m_routing_table; + Vector<LinkOrder> m_link_order; + int m_virtual_networks; + int m_round_robin_start; + int m_wakeups_wo_switch; + SimpleNetwork* m_network_ptr; +}; + +// Output operator declaration +ostream& operator<<(ostream& out, const PerfectSwitch& obj); + +// ******************* Definitions ******************* + +// Output operator definition +extern inline +ostream& operator<<(ostream& out, const PerfectSwitch& obj) +{ + obj.print(out); + out << flush; + return out; +} + +#endif //PerfectSwitch_H diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc new file mode 100644 index 000000000..549503e47 --- /dev/null +++ b/src/mem/ruby/network/simple/SimpleNetwork.cc @@ -0,0 +1,257 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * SimpleNetwork.C + * + * Description: See SimpleNetwork.h + * + * $Id$ + * + */ + +#include "SimpleNetwork.hh" +#include "Profiler.hh" +#include "System.hh" +#include "Switch.hh" +#include "NetDest.hh" +#include "Topology.hh" +#include "TopologyType.hh" +#include "MachineType.hh" +#include "MessageBuffer.hh" +#include "Protocol.hh" +#include "Map.hh" + +// ***BIG HACK*** - This is actually code that _should_ be in Network.C + +// Note: Moved to Princeton Network +// calls new to abstract away from the network +/* +Network* Network::createNetwork(int nodes) +{ + return new SimpleNetwork(nodes); +} +*/ + +SimpleNetwork::SimpleNetwork(int nodes) +{ + m_nodes = MachineType_base_number(MachineType_NUM); + + m_virtual_networks = NUMBER_OF_VIRTUAL_NETWORKS; + m_endpoint_switches.setSize(m_nodes); + + m_in_use.setSize(m_virtual_networks); + m_ordered.setSize(m_virtual_networks); + for (int i = 0; i < m_virtual_networks; i++) { + m_in_use[i] = false; + m_ordered[i] = false; + } + + // Allocate to and from queues + m_toNetQueues.setSize(m_nodes); + m_fromNetQueues.setSize(m_nodes); + for (int node = 0; node < m_nodes; node++) { + m_toNetQueues[node].setSize(m_virtual_networks); + m_fromNetQueues[node].setSize(m_virtual_networks); + for (int j = 0; j < m_virtual_networks; j++) { + m_toNetQueues[node][j] = new MessageBuffer; + m_fromNetQueues[node][j] = new MessageBuffer; + } + } + + // Setup the network switches + m_topology_ptr = new Topology(this, m_nodes); + int number_of_switches = m_topology_ptr->numSwitches(); + for (int i=0; i<number_of_switches; i++) { + m_switch_ptr_vector.insertAtBottom(new Switch(i, this)); + } + m_topology_ptr->createLinks(false); // false because this isn't a reconfiguration +} + +void SimpleNetwork::reset() +{ + for (int node = 0; node < m_nodes; node++) { + for (int j = 0; j < m_virtual_networks; j++) { + m_toNetQueues[node][j]->clear(); + m_fromNetQueues[node][j]->clear(); + } + } + + for(int i=0; i<m_switch_ptr_vector.size(); i++){ + m_switch_ptr_vector[i]->clearBuffers(); + } +} + +SimpleNetwork::~SimpleNetwork() +{ + for (int i = 0; i < m_nodes; i++) { + m_toNetQueues[i].deletePointers(); + m_fromNetQueues[i].deletePointers(); + } + m_switch_ptr_vector.deletePointers(); + m_buffers_to_free.deletePointers(); + delete m_topology_ptr; +} + +// From a switch to an endpoint node +void SimpleNetwork::makeOutLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration) +{ + assert(dest < m_nodes); + assert(src < m_switch_ptr_vector.size()); + assert(m_switch_ptr_vector[src] != NULL); + if(!isReconfiguration){ + m_switch_ptr_vector[src]->addOutPort(m_fromNetQueues[dest], routing_table_entry, link_latency, bw_multiplier); + m_endpoint_switches[dest] = m_switch_ptr_vector[src]; + } else { + m_switch_ptr_vector[src]->reconfigureOutPort(routing_table_entry); + } +} + +// From an endpoint node to a switch +void SimpleNetwork::makeInLink(NodeID src, SwitchID dest, const NetDest& routing_table_entry, int link_latency, int bw_multiplier, bool isReconfiguration) +{ + assert(src < m_nodes); + if(!isReconfiguration){ + m_switch_ptr_vector[dest]->addInPort(m_toNetQueues[src]); + } else { + // do nothing + } +} + +// From a switch to a switch +void SimpleNetwork::makeInternalLink(SwitchID src, SwitchID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration) +{ + if(!isReconfiguration){ + // Create a set of new MessageBuffers + Vector<MessageBuffer*> queues; + for (int i = 0; i < m_virtual_networks; i++) { + // allocate a buffer + MessageBuffer* buffer_ptr = new MessageBuffer; + buffer_ptr->setOrdering(true); + if(FINITE_BUFFERING) { + buffer_ptr->setSize(FINITE_BUFFER_SIZE); + } + queues.insertAtBottom(buffer_ptr); + // remember to deallocate it + m_buffers_to_free.insertAtBottom(buffer_ptr); + } + + // Connect it to the two switches + m_switch_ptr_vector[dest]->addInPort(queues); + m_switch_ptr_vector[src]->addOutPort(queues, routing_table_entry, link_latency, bw_multiplier); + } else { + m_switch_ptr_vector[src]->reconfigureOutPort(routing_table_entry); + } +} + +void SimpleNetwork::checkNetworkAllocation(NodeID id, bool ordered, int network_num) +{ + ASSERT(id < m_nodes); + ASSERT(network_num < m_virtual_networks); + + if (ordered) { + m_ordered[network_num] = true; + } + m_in_use[network_num] = true; +} + +MessageBuffer* SimpleNetwork::getToNetQueue(NodeID id, bool ordered, int network_num) +{ + checkNetworkAllocation(id, ordered, network_num); + return m_toNetQueues[id][network_num]; +} + +MessageBuffer* SimpleNetwork::getFromNetQueue(NodeID id, bool ordered, int network_num) +{ + checkNetworkAllocation(id, ordered, network_num); + return m_fromNetQueues[id][network_num]; +} + +const Vector<Throttle*>* SimpleNetwork::getThrottles(NodeID id) const +{ + assert(id >= 0); + assert(id < m_nodes); + assert(m_endpoint_switches[id] != NULL); + return m_endpoint_switches[id]->getThrottles(); +} + +void SimpleNetwork::printStats(ostream& out) const +{ + out << endl; + out << "Network Stats" << endl; + out << "-------------" << endl; + out << endl; + for(int i=0; i<m_switch_ptr_vector.size(); i++) { + m_switch_ptr_vector[i]->printStats(out); + } +} + +void SimpleNetwork::clearStats() +{ + for(int i=0; i<m_switch_ptr_vector.size(); i++) { + m_switch_ptr_vector[i]->clearStats(); + } +} + +void SimpleNetwork::printConfig(ostream& out) const +{ + out << endl; + out << "Network Configuration" << endl; + out << "---------------------" << endl; + out << "network: SIMPLE_NETWORK" << endl; + out << "topology: " << g_NETWORK_TOPOLOGY << endl; + out << endl; + + for (int i = 0; i < m_virtual_networks; i++) { + out << "virtual_net_" << i << ": "; + if (m_in_use[i]) { + out << "active, "; + if (m_ordered[i]) { + out << "ordered" << endl; + } else { + out << "unordered" << endl; + } + } else { + out << "inactive" << endl; + } + } + out << endl; + for(int i=0; i<m_switch_ptr_vector.size(); i++) { + m_switch_ptr_vector[i]->printConfig(out); + } + + if (g_PRINT_TOPOLOGY) { + m_topology_ptr->printConfig(out); + } +} + +void SimpleNetwork::print(ostream& out) const +{ + out << "[SimpleNetwork]"; +} diff --git a/src/mem/ruby/network/simple/SimpleNetwork.hh b/src/mem/ruby/network/simple/SimpleNetwork.hh new file mode 100644 index 000000000..a28904227 --- /dev/null +++ b/src/mem/ruby/network/simple/SimpleNetwork.hh @@ -0,0 +1,157 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * SimpleNetwork.h + * + * Description: The SimpleNetwork class implements the interconnection + * SimpleNetwork between components (processor/cache components and + * memory/directory components). The interconnection network as + * described here is not a physical network, but a programming concept + * used to implement all communication between components. Thus parts + * of this 'network' may model the on-chip connections between cache + * controllers and directory controllers as well as the links between + * chip and network switches. + * + * Two conceptual networks, an address and data network, are modeled. + * The data network is unordered, where the address network provides + * and conforms to a global ordering of all transactions. + * + * Currently the data network is point-to-point and the address + * network is a broadcast network. These two distinct conceptual + * network can be modeled as physically separate networks or + * multiplexed over a single physical network. + * + * The network encapsulates all notion of virtual global time and is + * responsible for ordering the network transactions received. This + * hides all of these ordering details from the processor/cache and + * directory/memory modules. + * + * FIXME: Various flavor of networks are provided as a compiler time + * configurable. We currently include this SimpleNetwork in the + * makefile's vpath, so that SimpleNetwork.C can provide an alternative + * version constructor for the abstract Network class. It is easy to + * modify this to make network a runtime configuable. Just make the + * abstract Network class take a enumeration parameter, and based on + * that to initial proper network. Or even better, just make the ruby + * system initializer choose the proper network to initiate. + * + * $Id$ + * + */ + +#ifndef SIMPLENETWORK_H +#define SIMPLENETWORK_H + +#include "Global.hh" +#include "Vector.hh" +#include "Network.hh" +#include "NodeID.hh" + +class NetDest; +class MessageBuffer; +class Throttle; +class Switch; +class Topology; + +class SimpleNetwork : public Network { +public: + // Constructors + SimpleNetwork(int nodes); + + // Destructor + ~SimpleNetwork(); + + // Public Methods + void printStats(ostream& out) const; + void clearStats(); + void printConfig(ostream& out) const; + + void reset(); + + // returns the queue requested for the given component + MessageBuffer* getToNetQueue(NodeID id, bool ordered, int network_num); + MessageBuffer* getFromNetQueue(NodeID id, bool ordered, int network_num); + virtual const Vector<Throttle*>* getThrottles(NodeID id) const; + + bool isVNetOrdered(int vnet) { return m_ordered[vnet]; } + bool validVirtualNetwork(int vnet) { return m_in_use[vnet]; } + + int getNumNodes() {return m_nodes; } + + // Methods used by Topology to setup the network + void makeOutLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration); + void makeInLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int bw_multiplier, bool isReconfiguration); + void makeInternalLink(SwitchID src, NodeID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration); + + void print(ostream& out) const; +private: + void checkNetworkAllocation(NodeID id, bool ordered, int network_num); + void addLink(SwitchID src, SwitchID dest, int link_latency); + void makeLink(SwitchID src, SwitchID dest, const NetDest& routing_table_entry, int link_latency); + SwitchID createSwitch(); + void makeTopology(); + void linkTopology(); + + + // Private copy constructor and assignment operator + SimpleNetwork(const SimpleNetwork& obj); + SimpleNetwork& operator=(const SimpleNetwork& obj); + + // Data Members (m_ prefix) + + // vector of queues from the components + Vector<Vector<MessageBuffer*> > m_toNetQueues; + Vector<Vector<MessageBuffer*> > m_fromNetQueues; + + int m_nodes; + int m_virtual_networks; + Vector<bool> m_in_use; + Vector<bool> m_ordered; + Vector<Switch*> m_switch_ptr_vector; + Vector<MessageBuffer*> m_buffers_to_free; + Vector<Switch*> m_endpoint_switches; + Topology* m_topology_ptr; +}; + +// Output operator declaration +ostream& operator<<(ostream& out, const SimpleNetwork& obj); + +// ******************* Definitions ******************* + +// Output operator definition +extern inline +ostream& operator<<(ostream& out, const SimpleNetwork& obj) +{ + obj.print(out); + out << flush; + return out; +} + +#endif //SIMPLENETWORK_H diff --git a/src/mem/ruby/network/simple/Switch.cc b/src/mem/ruby/network/simple/Switch.cc new file mode 100644 index 000000000..3b55d156f --- /dev/null +++ b/src/mem/ruby/network/simple/Switch.cc @@ -0,0 +1,205 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Switch.C + * + * Description: See Switch.h + * + * $Id$ + * + */ + + +#include "Switch.hh" +#include "PerfectSwitch.hh" +#include "MessageBuffer.hh" +#include "Throttle.hh" +#include "MessageSizeType.hh" +#include "Network.hh" +#include "Protocol.hh" + +Switch::Switch(SwitchID sid, SimpleNetwork* network_ptr) +{ + m_perfect_switch_ptr = new PerfectSwitch(sid, network_ptr); + m_switch_id = sid; + m_throttles.setSize(0); +} + +Switch::~Switch() +{ + delete m_perfect_switch_ptr; + + // Delete throttles (one per output port) + m_throttles.deletePointers(); + + // Delete MessageBuffers + m_buffers_to_free.deletePointers(); +} + +void Switch::addInPort(const Vector<MessageBuffer*>& in) +{ + m_perfect_switch_ptr->addInPort(in); +} + +void Switch::addOutPort(const Vector<MessageBuffer*>& out, const NetDest& routing_table_entry, int link_latency, int bw_multiplier) +{ + Throttle* throttle_ptr = NULL; + + // Create a throttle + throttle_ptr = new Throttle(m_switch_id, m_throttles.size(), link_latency, bw_multiplier); + m_throttles.insertAtBottom(throttle_ptr); + + // Create one buffer per vnet (these are intermediaryQueues) + Vector<MessageBuffer*> intermediateBuffers; + for (int i=0; i<out.size(); i++) { + MessageBuffer* buffer_ptr = new MessageBuffer; + // Make these queues ordered + buffer_ptr->setOrdering(true); + if(FINITE_BUFFERING) { + buffer_ptr->setSize(FINITE_BUFFER_SIZE); + } + intermediateBuffers.insertAtBottom(buffer_ptr); + m_buffers_to_free.insertAtBottom(buffer_ptr); + } + + // Hook the queues to the PerfectSwitch + m_perfect_switch_ptr->addOutPort(intermediateBuffers, routing_table_entry); + + // Hook the queues to the Throttle + throttle_ptr->addLinks(intermediateBuffers, out); + +} + +void Switch::clearRoutingTables() +{ + m_perfect_switch_ptr->clearRoutingTables(); +} + +void Switch::clearBuffers() +{ + m_perfect_switch_ptr->clearBuffers(); + for (int i=0; i<m_throttles.size(); i++) { + if (m_throttles[i] != NULL) { + m_throttles[i]->clear(); + } + } +} + +void Switch::reconfigureOutPort(const NetDest& routing_table_entry) +{ + m_perfect_switch_ptr->reconfigureOutPort(routing_table_entry); +} + +const Throttle* Switch::getThrottle(LinkID link_number) const +{ + assert(m_throttles[link_number] != NULL); + return m_throttles[link_number]; +} + +const Vector<Throttle*>* Switch::getThrottles() const +{ + return &m_throttles; +} + +void Switch::printStats(ostream& out) const +{ + out << "switch_" << m_switch_id << "_inlinks: " << m_perfect_switch_ptr->getInLinks() << endl; + out << "switch_" << m_switch_id << "_outlinks: " << m_perfect_switch_ptr->getOutLinks() << endl; + + // Average link utilizations + double average_utilization = 0.0; + int throttle_count = 0; + + for (int i=0; i<m_throttles.size(); i++) { + Throttle* throttle_ptr = m_throttles[i]; + if (throttle_ptr != NULL) { + average_utilization += throttle_ptr->getUtilization(); + throttle_count++; + } + } + average_utilization = (throttle_count == 0) ? 0 : average_utilization / float(throttle_count); + + // Individual link utilizations + out << "links_utilized_percent_switch_" << m_switch_id << ": " << average_utilization << endl; + for (int link=0; link<m_throttles.size(); link++) { + Throttle* throttle_ptr = m_throttles[link]; + if (throttle_ptr != NULL) { + out << " links_utilized_percent_switch_" << m_switch_id << "_link_" << link << ": " + << throttle_ptr->getUtilization() << " bw: " << throttle_ptr->getLinkBandwidth() + << " base_latency: " << throttle_ptr->getLatency() << endl; + } + } + out << endl; + + // Traffic breakdown + for (int link=0; link<m_throttles.size(); link++) { + Throttle* throttle_ptr = m_throttles[link]; + if (throttle_ptr != NULL) { + const Vector<Vector<int> >& message_counts = throttle_ptr->getCounters(); + for (int int_type=0; int_type<MessageSizeType_NUM; int_type++) { + MessageSizeType type = MessageSizeType(int_type); + int sum = message_counts[type].sum(); + if (sum != 0) { + out << " outgoing_messages_switch_" << m_switch_id << "_link_" << link << "_" << type + << ": " << sum << " " << sum * MessageSizeType_to_int(type) + << " " << message_counts[type] << " base_latency: " << throttle_ptr->getLatency() << endl; + } + } + } + } + out << endl; +} + +void Switch::clearStats() +{ + m_perfect_switch_ptr->clearStats(); + for (int i=0; i<m_throttles.size(); i++) { + if (m_throttles[i] != NULL) { + m_throttles[i]->clearStats(); + } + } +} + +void Switch::printConfig(ostream& out) const +{ + m_perfect_switch_ptr->printConfig(out); + for (int i=0; i<m_throttles.size(); i++) { + if (m_throttles[i] != NULL) { + m_throttles[i]->printConfig(out); + } + } +} + +void Switch::print(ostream& out) const +{ + // FIXME printing + out << "[Switch]"; +} + diff --git a/src/mem/ruby/network/simple/Switch.hh b/src/mem/ruby/network/simple/Switch.hh new file mode 100644 index 000000000..a408155c0 --- /dev/null +++ b/src/mem/ruby/network/simple/Switch.hh @@ -0,0 +1,105 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $Id$ + * + * Description: The actual modelled switch. It use the perfect switch and a + * Throttle object to control and bandwidth and timing *only for + * the output port*. So here we have un-realistic modelling, + * since the order of PerfectSwitch and Throttle objects get + * woke up affect the message timing. A more accurate model would + * be having two set of system states, one for this cycle, one for + * next cycle. And on the cycle boundary swap the two set of + * states. + * + */ + +#ifndef Switch_H +#define Switch_H + +#include "Global.hh" +#include "Vector.hh" + +class MessageBuffer; +class PerfectSwitch; +class NetDest; +class SimpleNetwork; +class Throttle; + +class Switch { +public: + // Constructors + + // constructor specifying the number of ports + Switch(SwitchID sid, SimpleNetwork* network_ptr); + void addInPort(const Vector<MessageBuffer*>& in); + void addOutPort(const Vector<MessageBuffer*>& out, const NetDest& routing_table_entry, int link_latency, int bw_multiplier); + const Throttle* getThrottle(LinkID link_number) const; + const Vector<Throttle*>* getThrottles() const; + void clearRoutingTables(); + void clearBuffers(); + void reconfigureOutPort(const NetDest& routing_table_entry); + + void printStats(ostream& out) const; + void clearStats(); + void printConfig(ostream& out) const; + + // Destructor + ~Switch(); + + void print(ostream& out) const; +private: + + // Private copy constructor and assignment operator + Switch(const Switch& obj); + Switch& operator=(const Switch& obj); + + // Data Members (m_ prefix) + PerfectSwitch* m_perfect_switch_ptr; + Vector<Throttle*> m_throttles; + Vector<MessageBuffer*> m_buffers_to_free; + SwitchID m_switch_id; +}; + +// Output operator declaration +ostream& operator<<(ostream& out, const Switch& obj); + +// ******************* Definitions ******************* + +// Output operator definition +extern inline +ostream& operator<<(ostream& out, const Switch& obj) +{ + obj.print(out); + out << flush; + return out; +} + +#endif //Switch_H diff --git a/src/mem/ruby/network/simple/Throttle.cc b/src/mem/ruby/network/simple/Throttle.cc new file mode 100644 index 000000000..2f6e68afd --- /dev/null +++ b/src/mem/ruby/network/simple/Throttle.cc @@ -0,0 +1,291 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $Id$ + * + * Description: see Throttle.h + * + */ + +#include "Throttle.hh" +#include "MessageBuffer.hh" +#include "Network.hh" +#include "System.hh" +#include "NetworkMessage.hh" +#include "Protocol.hh" + +const int HIGH_RANGE = 256; +const int ADJUST_INTERVAL = 50000; +const int MESSAGE_SIZE_MULTIPLIER = 1000; +//const int BROADCAST_SCALING = 4; // Have a 16p system act like a 64p systems +const int BROADCAST_SCALING = 1; +const int PRIORITY_SWITCH_LIMIT = 128; + +static int network_message_to_size(NetworkMessage* net_msg_ptr); + +extern std::ostream * debug_cout_ptr; + +Throttle::Throttle(int sID, NodeID node, int link_latency, int link_bandwidth_multiplier) +{ + init(node, link_latency, link_bandwidth_multiplier); + m_sID = sID; +} + +Throttle::Throttle(NodeID node, int link_latency, int link_bandwidth_multiplier) +{ + init(node, link_latency, link_bandwidth_multiplier); + m_sID = 0; +} + +void Throttle::init(NodeID node, int link_latency, int link_bandwidth_multiplier) +{ + m_node = node; + m_vnets = 0; + + ASSERT(link_bandwidth_multiplier > 0); + m_link_bandwidth_multiplier = link_bandwidth_multiplier; + m_link_latency = link_latency; + + m_bash_counter = HIGH_RANGE; + m_bandwidth_since_sample = 0; + m_last_bandwidth_sample = 0; + m_wakeups_wo_switch = 0; + clearStats(); +} + +void Throttle::clear() +{ + for (int counter = 0; counter < m_vnets; counter++) { + m_in[counter]->clear(); + m_out[counter]->clear(); + } +} + +void Throttle::addLinks(const Vector<MessageBuffer*>& in_vec, const Vector<MessageBuffer*>& out_vec) +{ + assert(in_vec.size() == out_vec.size()); + for (int i=0; i<in_vec.size(); i++) { + addVirtualNetwork(in_vec[i], out_vec[i]); + } + + m_message_counters.setSize(MessageSizeType_NUM); + for (int i=0; i<MessageSizeType_NUM; i++) { + m_message_counters[i].setSize(in_vec.size()); + for (int j=0; j<m_message_counters[i].size(); j++) { + m_message_counters[i][j] = 0; + } + } + + if (g_PRINT_TOPOLOGY) { + m_out_link_vec.insertAtBottom(out_vec); + } +} + +void Throttle::addVirtualNetwork(MessageBuffer* in_ptr, MessageBuffer* out_ptr) +{ + m_units_remaining.insertAtBottom(0); + m_in.insertAtBottom(in_ptr); + m_out.insertAtBottom(out_ptr); + + // Set consumer and description + m_in[m_vnets]->setConsumer(this); + string desc = "[Queue to Throttle " + NodeIDToString(m_sID) + " " + NodeIDToString(m_node) + "]"; + m_in[m_vnets]->setDescription(desc); + m_vnets++; +} + +void Throttle::wakeup() +{ + // Limits the number of message sent to a limited number of bytes/cycle. + assert(getLinkBandwidth() > 0); + int bw_remaining = getLinkBandwidth(); + + // Give the highest numbered link priority most of the time + m_wakeups_wo_switch++; + int highest_prio_vnet = m_vnets-1; + int lowest_prio_vnet = 0; + int counter = 1; + bool schedule_wakeup = false; + + // invert priorities to avoid starvation seen in the component network + if (m_wakeups_wo_switch > PRIORITY_SWITCH_LIMIT) { + m_wakeups_wo_switch = 0; + highest_prio_vnet = 0; + lowest_prio_vnet = m_vnets-1; + counter = -1; + } + + for (int vnet = highest_prio_vnet; (vnet*counter) >= (counter*lowest_prio_vnet); vnet -= counter) { + + assert(m_out[vnet] != NULL); + assert(m_in[vnet] != NULL); + assert(m_units_remaining[vnet] >= 0); + + while ((bw_remaining > 0) && ((m_in[vnet]->isReady()) || (m_units_remaining[vnet] > 0)) && m_out[vnet]->areNSlotsAvailable(1)) { + + // See if we are done transferring the previous message on this virtual network + if (m_units_remaining[vnet] == 0 && m_in[vnet]->isReady()) { + + // Find the size of the message we are moving + MsgPtr msg_ptr = m_in[vnet]->peekMsgPtr(); + NetworkMessage* net_msg_ptr = dynamic_cast<NetworkMessage*>(msg_ptr.ref()); + m_units_remaining[vnet] += network_message_to_size(net_msg_ptr); + + DEBUG_NEWLINE(NETWORK_COMP,HighPrio); + DEBUG_MSG(NETWORK_COMP,HighPrio,"throttle: " + int_to_string(m_node) + + " my bw " + int_to_string(getLinkBandwidth()) + + " bw spent enqueueing net msg " + int_to_string(m_units_remaining[vnet]) + + " time: " + int_to_string(g_eventQueue_ptr->getTime()) + "."); + + // Move the message + m_out[vnet]->enqueue(m_in[vnet]->peekMsgPtr(), m_link_latency); + m_in[vnet]->pop(); + + // Count the message + m_message_counters[net_msg_ptr->getMessageSize()][vnet]++; + + DEBUG_MSG(NETWORK_COMP,LowPrio,*m_out[vnet]); + DEBUG_NEWLINE(NETWORK_COMP,HighPrio); + } + + // Calculate the amount of bandwidth we spent on this message + int diff = m_units_remaining[vnet] - bw_remaining; + m_units_remaining[vnet] = max(0, diff); + bw_remaining = max(0, -diff); + } + + if ((bw_remaining > 0) && ((m_in[vnet]->isReady()) || (m_units_remaining[vnet] > 0)) && !m_out[vnet]->areNSlotsAvailable(1)) { + DEBUG_MSG(NETWORK_COMP,LowPrio,vnet); + schedule_wakeup = true; // schedule me to wakeup again because I'm waiting for my output queue to become available + } + } + + // We should only wake up when we use the bandwidth + // assert(bw_remaining != getLinkBandwidth()); // This is only mostly true + + // Record that we used some or all of the link bandwidth this cycle + double ratio = 1.0-(double(bw_remaining)/double(getLinkBandwidth())); + // If ratio = 0, we used no bandwidth, if ratio = 1, we used all + linkUtilized(ratio); + + // Sample the link bandwidth utilization over a number of cycles + int bw_used = getLinkBandwidth()-bw_remaining; + m_bandwidth_since_sample += bw_used; + + // FIXME - comment out the bash specific code for faster performance + // Start Bash code + // Update the predictor + Time current_time = g_eventQueue_ptr->getTime(); + while ((current_time - m_last_bandwidth_sample) > ADJUST_INTERVAL) { + double utilization = m_bandwidth_since_sample/double(ADJUST_INTERVAL * getLinkBandwidth()); + + if (utilization > g_bash_bandwidth_adaptive_threshold) { + // Used more bandwidth + m_bash_counter++; + } else { + // Used less bandwidth + m_bash_counter--; + } + + // Make sure we don't overflow + m_bash_counter = min(HIGH_RANGE, m_bash_counter); + m_bash_counter = max(0, m_bash_counter); + + // Reset samples + m_last_bandwidth_sample += ADJUST_INTERVAL; + m_bandwidth_since_sample = 0; + } + // End Bash code + + if ((bw_remaining > 0) && !schedule_wakeup) { + // We have extra bandwidth and our output buffer was available, so we must not have anything else to do until another message arrives. + DEBUG_MSG(NETWORK_COMP,LowPrio,*this); + DEBUG_MSG(NETWORK_COMP,LowPrio,"not scheduled again"); + } else { + DEBUG_MSG(NETWORK_COMP,LowPrio,*this); + DEBUG_MSG(NETWORK_COMP,LowPrio,"scheduled again"); + // We are out of bandwidth for this cycle, so wakeup next cycle and continue + g_eventQueue_ptr->scheduleEvent(this, 1); + } +} + +bool Throttle::broadcastBandwidthAvailable(int rand) const +{ + bool result = !(m_bash_counter > ((HIGH_RANGE/4) + (rand % (HIGH_RANGE/2)))); + return result; +} + +void Throttle::printStats(ostream& out) const +{ + out << "utilized_percent: " << getUtilization() << endl; +} + +void Throttle::clearStats() +{ + m_ruby_start = g_eventQueue_ptr->getTime(); + m_links_utilized = 0.0; + + for (int i=0; i<m_message_counters.size(); i++) { + for (int j=0; j<m_message_counters[i].size(); j++) { + m_message_counters[i][j] = 0; + } + } +} + +void Throttle::printConfig(ostream& out) const +{ + +} + +double Throttle::getUtilization() const +{ + return (100.0 * double(m_links_utilized)) / (double(g_eventQueue_ptr->getTime()-m_ruby_start)); +} + +void Throttle::print(ostream& out) const +{ + out << "[Throttle: " << m_sID << " " << m_node << " bw: " << getLinkBandwidth() << "]"; +} + +// Helper function + +static +int network_message_to_size(NetworkMessage* net_msg_ptr) +{ + assert(net_msg_ptr != NULL); + + // Artificially increase the size of broadcast messages + if (BROADCAST_SCALING > 1) { + if (net_msg_ptr->getDestination().isBroadcast()) { + return (MessageSizeType_to_int(net_msg_ptr->getMessageSize()) * MESSAGE_SIZE_MULTIPLIER * BROADCAST_SCALING); + } + } + return (MessageSizeType_to_int(net_msg_ptr->getMessageSize()) * MESSAGE_SIZE_MULTIPLIER); +} diff --git a/src/mem/ruby/network/simple/Throttle.hh b/src/mem/ruby/network/simple/Throttle.hh new file mode 100644 index 000000000..67cfabcdc --- /dev/null +++ b/src/mem/ruby/network/simple/Throttle.hh @@ -0,0 +1,124 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $Id$ + * + * Description: The class to implement bandwidth and latency throttle. An + * instance of consumer class that can be woke up. It is only used + * to control bandwidth at output port of a switch. And the + * throttle is added *after* the output port, means the message is + * put in the output port of the PerfectSwitch (a + * intermediateBuffers) first, then go through the Throttle. + * + */ + +#ifndef THROTTLE_H +#define THROTTLE_H + +#include "Global.hh" +#include "Vector.hh" +#include "Consumer.hh" +#include "NodeID.hh" +#include "RubyConfig.hh" + +class MessageBuffer; + +class Throttle : public Consumer { +public: + // Constructors + Throttle(int sID, NodeID node, int link_latency, int link_bandwidth_multiplier); + Throttle(NodeID node, int link_latency, int link_bandwidth_multiplier); + + // Destructor + ~Throttle() {} + + // Public Methods + void addLinks(const Vector<MessageBuffer*>& in_vec, const Vector<MessageBuffer*>& out_vec); + void wakeup(); + bool broadcastBandwidthAvailable(int rand) const; + + void printStats(ostream& out) const; + void clearStats(); + void printConfig(ostream& out) const; + double getUtilization() const; // The average utilization (a percent) since last clearStats() + int getLinkBandwidth() const { return g_endpoint_bandwidth * m_link_bandwidth_multiplier; } + int getLatency() const { return m_link_latency; } + + const Vector<Vector<int> >& getCounters() const { return m_message_counters; } + + void clear(); + + void print(ostream& out) const; + +private: + // Private Methods + void init(NodeID node, int link_latency, int link_bandwidth_multiplier); + void addVirtualNetwork(MessageBuffer* in_ptr, MessageBuffer* out_ptr); + void linkUtilized(double ratio) { m_links_utilized += ratio; } + + // Private copy constructor and assignment operator + Throttle(const Throttle& obj); + Throttle& operator=(const Throttle& obj); + + // Data Members (m_ prefix) + Vector<MessageBuffer*> m_in; + Vector<MessageBuffer*> m_out; + Vector<Vector<int> > m_message_counters; + int m_vnets; + Vector<int> m_units_remaining; + int m_sID; + NodeID m_node; + int m_bash_counter; + int m_bandwidth_since_sample; + Time m_last_bandwidth_sample; + int m_link_bandwidth_multiplier; + int m_link_latency; + int m_wakeups_wo_switch; + + // For tracking utilization + Time m_ruby_start; + double m_links_utilized; +}; + +// Output operator declaration +ostream& operator<<(ostream& out, const Throttle& obj); + +// ******************* Definitions ******************* + +// Output operator definition +extern inline +ostream& operator<<(ostream& out, const Throttle& obj) +{ + obj.print(out); + out << flush; + return out; +} + +#endif //THROTTLE_H diff --git a/src/mem/ruby/network/simple/Topology.cc b/src/mem/ruby/network/simple/Topology.cc new file mode 100644 index 000000000..db886052f --- /dev/null +++ b/src/mem/ruby/network/simple/Topology.cc @@ -0,0 +1,801 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Topology.C + * + * Description: See Topology.h + * + * $Id$ + * + * */ + +#include "Topology.hh" +#include "NetDest.hh" +#include "Network.hh" +#include "TopologyType.hh" +#include "RubyConfig.hh" +#include "util.hh" +#include "MachineType.hh" +#include "Protocol.hh" +#include <string> + +static const int INFINITE_LATENCY = 10000; // Yes, this is a big hack +static const int DEFAULT_BW_MULTIPLIER = 1; // Just to be consistent with above :) + +// Note: In this file, we use the first 2*m_nodes SwitchIDs to +// represent the input and output endpoint links. These really are +// not 'switches', as they will not have a Switch object allocated for +// them. The first m_nodes SwitchIDs are the links into the network, +// the second m_nodes set of SwitchIDs represent the the output queues +// of the network. + +// Helper functions based on chapter 29 of Cormen et al. +static Matrix extend_shortest_path(const Matrix& current_dist, Matrix& latencies, Matrix& inter_switches); +static Matrix shortest_path(const Matrix& weights, Matrix& latencies, Matrix& inter_switches); +static bool link_is_shortest_path_to_node(SwitchID src, SwitchID next, SwitchID final, const Matrix& weights, const Matrix& dist); +static NetDest shortest_path_to_node(SwitchID src, SwitchID next, const Matrix& weights, const Matrix& dist); + + +Topology::Topology(Network* network_ptr, int number_of_nodes) +{ + m_network_ptr = network_ptr; + m_nodes = number_of_nodes; + m_number_of_switches = 0; + init(); +} + +void Topology::init() +{ + if (m_nodes == 1) { + SwitchID id = newSwitchID(); + addLink(0, id, NETWORK_LINK_LATENCY); + addLink(id, 1, NETWORK_LINK_LATENCY); + return; + } + + // topology-specific set-up + TopologyType topology = string_to_TopologyType(g_NETWORK_TOPOLOGY); + switch (topology) { + case TopologyType_TORUS_2D: + make2DTorus(); + break; + case TopologyType_HIERARCHICAL_SWITCH: + makeHierarchicalSwitch(FAN_OUT_DEGREE); + break; + case TopologyType_CROSSBAR: + makeHierarchicalSwitch(1024); + break; + case TopologyType_PT_TO_PT: + makePtToPt(); + break; + case TopologyType_FILE_SPECIFIED: + makeFileSpecified(); + break; + default: + ERROR_MSG("Unexpected typology type") + } + + // initialize component latencies record + m_component_latencies.setSize(0); + m_component_inter_switches.setSize(0); +} + +void Topology::makeSwitchesPerChip(Vector< Vector < SwitchID > > &nodePairs, Vector<int> &latencies, Vector<int> &bw_multis, int numberOfChipSwitches) +{ + + Vector < SwitchID > nodes; // temporary buffer + nodes.setSize(2); + + Vector<bool> endpointConnectionExist; // used to ensure all endpoints are connected to the network + endpointConnectionExist.setSize(m_nodes); + // initialize endpoint check vector + for (int k = 0; k < endpointConnectionExist.size(); k++) { + endpointConnectionExist[k] = false; + } + + Vector<int> componentCount; + componentCount.setSize(MachineType_NUM); + for (MachineType mType = MachineType_FIRST; mType < MachineType_NUM; ++mType) { + componentCount[mType] = 0; + } + + // components to/from network links + for (int chip = 0; chip < RubyConfig::numberOfChips(); chip++) { + for (MachineType mType = MachineType_FIRST; mType < MachineType_NUM; ++mType) { + for (int component = 0; component < MachineType_chip_count(mType, chip); component++) { + + int latency = -1; + int bw_multiplier = -1; // internal link bw multiplier of the global bandwidth + if (mType != MachineType_Directory) { + latency = ON_CHIP_LINK_LATENCY; // internal link latency + bw_multiplier = 10; // internal link bw multiplier of the global bandwidth + } else { + latency = NETWORK_LINK_LATENCY; // local memory latency + bw_multiplier = 1; // local memory link bw multiplier of the global bandwidth + } + nodes[0] = MachineType_base_number(mType)+componentCount[mType]; + nodes[1] = chip+m_nodes*2; // this is the chip's internal switch id # + + // insert link + nodePairs.insertAtBottom(nodes); + latencies.insertAtBottom(latency); + //bw_multis.insertAtBottom(bw_multiplier); + bw_multis.insertAtBottom(componentCount[mType]+MachineType_base_number((MachineType)mType)); + + // opposite direction link + Vector < SwitchID > otherDirectionNodes; + otherDirectionNodes.setSize(2); + otherDirectionNodes[0] = nodes[1]; + otherDirectionNodes[1] = nodes[0]+m_nodes; + nodePairs.insertAtBottom(otherDirectionNodes); + latencies.insertAtBottom(latency); + bw_multis.insertAtBottom(bw_multiplier); + + assert(!endpointConnectionExist[nodes[0]]); + endpointConnectionExist[nodes[0]] = true; + componentCount[mType]++; + } + } + } + + // make sure all enpoints are connected in the soon to be created network + for (int k = 0; k < endpointConnectionExist.size(); k++) { + if (endpointConnectionExist[k] == false) { + cerr << "Error: Unconnected Endpoint: " << k << endl; + exit(1); + } + } + + // secondary check to ensure we saw the correct machine counts + for (MachineType mType = MachineType_FIRST; mType < MachineType_NUM; ++mType) { + assert(componentCount[mType] == MachineType_base_count((MachineType)mType)); + } + +} + +// 2D torus topology + +void Topology::make2DTorus() +{ + Vector< Vector < SwitchID > > nodePairs; // node pairs extracted from the file + Vector<int> latencies; // link latencies for each link extracted + Vector<int> bw_multis; // bw multipliers for each link extracted + + Vector < SwitchID > nodes; // temporary buffer + nodes.setSize(2); + + // number of inter-chip switches + int numberOfTorusSwitches = m_nodes/MachineType_base_level(MachineType_NUM); + // one switch per machine node grouping + Vector<SwitchID> torusSwitches; + for(int i=0; i<numberOfTorusSwitches; i++){ + SwitchID new_switch = newSwitchID(); + torusSwitches.insertAtBottom(new_switch); + } + + makeSwitchesPerChip(nodePairs, latencies, bw_multis, numberOfTorusSwitches); + + int lengthOfSide = (int)sqrt((double)numberOfTorusSwitches); + + // Now connect the inter-chip torus links + + int latency = NETWORK_LINK_LATENCY; // external link latency + int bw_multiplier = 1; // external link bw multiplier of the global bandwidth + + for(int i=0; i<numberOfTorusSwitches; i++){ + nodes[0] = torusSwitches[i]; // current switch + + // left + if(nodes[0]%lengthOfSide == 0){ // determine left neighbor + nodes[1] = nodes[0] - 1 + lengthOfSide; + } else { + nodes[1] = nodes[0] - 1; + } + nodePairs.insertAtBottom(nodes); + latencies.insertAtBottom(latency); + bw_multis.insertAtBottom(bw_multiplier); + + // right + if((nodes[0] + 1)%lengthOfSide == 0){ // determine right neighbor + nodes[1] = nodes[0] + 1 - lengthOfSide; + } else { + nodes[1] = nodes[0] + 1; + } + nodePairs.insertAtBottom(nodes); + latencies.insertAtBottom(latency); + bw_multis.insertAtBottom(bw_multiplier); + + // top + if(nodes[0] - lengthOfSide < 2*m_nodes){ // determine if node is on the top + nodes[1] = nodes[0] - lengthOfSide + (lengthOfSide*lengthOfSide); + } else { + nodes[1] = nodes[0] - lengthOfSide; + } + nodePairs.insertAtBottom(nodes); + latencies.insertAtBottom(latency); + bw_multis.insertAtBottom(bw_multiplier); + + // bottom + if(nodes[0] + lengthOfSide >= 2*m_nodes+numberOfTorusSwitches){ // determine if node is on the bottom + // sorin: bad bug if this is a > instead of a >= + nodes[1] = nodes[0] + lengthOfSide - (lengthOfSide*lengthOfSide); + } else { + nodes[1] = nodes[0] + lengthOfSide; + } + nodePairs.insertAtBottom(nodes); + latencies.insertAtBottom(latency); + bw_multis.insertAtBottom(bw_multiplier); + + } + + // add links + ASSERT(nodePairs.size() == latencies.size() && latencies.size() == bw_multis.size()) + for (int k = 0; k < nodePairs.size(); k++) { + ASSERT(nodePairs[k].size() == 2); + addLink(nodePairs[k][0], nodePairs[k][1], latencies[k], bw_multis[k]); + } + +} + +// hierarchical switch topology +void Topology::makeHierarchicalSwitch(int fan_out_degree) +{ + // Make a row of switches with only one input. This extra row makes + // sure the links out of the nodes have latency and limited + // bandwidth. + + // number of inter-chip switches, i.e. the last row of switches + Vector<SwitchID> last_level; + for (int i=0; i<m_nodes; i++) { + SwitchID new_switch = newSwitchID(); // internal switch id # + addLink(i, new_switch, NETWORK_LINK_LATENCY); + last_level.insertAtBottom(new_switch); + } + + // Create Hierarchical Switches + + // start from the bottom level and work up to root + Vector<SwitchID> next_level; + while(last_level.size() > 1) { + for (int i=0; i<last_level.size(); i++) { + if ((i % fan_out_degree) == 0) { + next_level.insertAtBottom(newSwitchID()); + } + // Add this link to the last switch we created + addLink(last_level[i], next_level[next_level.size()-1], NETWORK_LINK_LATENCY); + } + + // Make the current level the last level to get ready for next + // iteration + last_level = next_level; + next_level.clear(); + } + + SwitchID root_switch = last_level[0]; + + Vector<SwitchID> out_level; + for (int i=0; i<m_nodes; i++) { + out_level.insertAtBottom(m_nodes+i); + } + + // Build the down network from the endpoints to the root + while(out_level.size() != 1) { + + // A level of switches + for (int i=0; i<out_level.size(); i++) { + if ((i % fan_out_degree) == 0) { + if (out_level.size() > fan_out_degree) { + next_level.insertAtBottom(newSwitchID()); + } else { + next_level.insertAtBottom(root_switch); + } + } + // Add this link to the last switch we created + addLink(next_level[next_level.size()-1], out_level[i], NETWORK_LINK_LATENCY); + } + + // Make the current level the last level to get ready for next + // iteration + out_level = next_level; + next_level.clear(); + } +} + +// one internal node per chip, point to point links between chips +void Topology::makePtToPt() +{ + Vector< Vector < SwitchID > > nodePairs; // node pairs extracted from the file + Vector<int> latencies; // link latencies for each link extracted + Vector<int> bw_multis; // bw multipliers for each link extracted + + Vector < SwitchID > nodes; + nodes.setSize(2); + + // number of inter-chip switches + int numberOfChipSwitches = m_nodes/MachineType_base_level(MachineType_NUM); + // two switches per machine node grouping + // one intra-chip switch and one inter-chip switch per chip + for(int i=0; i<numberOfChipSwitches; i++){ + SwitchID new_switch = newSwitchID(); + new_switch = newSwitchID(); + } + + makeSwitchesPerChip(nodePairs, latencies, bw_multis, numberOfChipSwitches); + + // connect intra-chip switch to inter-chip switch + for (int chip = 0; chip < RubyConfig::numberOfChips(); chip++) { + + int latency = ON_CHIP_LINK_LATENCY; // internal link latency + int bw_multiplier = 10; // external link bw multiplier of the global bandwidth + + nodes[0] = chip+m_nodes*2; + nodes[1] = chip+m_nodes*2+RubyConfig::numberOfChips(); + + // insert link + nodePairs.insertAtBottom(nodes); + latencies.insertAtBottom(latency); + bw_multis.insertAtBottom(bw_multiplier); + + // opposite direction link + Vector < SwitchID > otherDirectionNodes; + otherDirectionNodes.setSize(2); + otherDirectionNodes[0] = nodes[1]; + otherDirectionNodes[1] = nodes[0]; + nodePairs.insertAtBottom(otherDirectionNodes); + latencies.insertAtBottom(latency); + bw_multis.insertAtBottom(bw_multiplier); + } + + // point-to-point network between chips + for (int chip = 0; chip < RubyConfig::numberOfChips(); chip++) { + for (int other_chip = chip+1; other_chip < RubyConfig::numberOfChips(); other_chip++) { + + int latency = NETWORK_LINK_LATENCY; // external link latency + int bw_multiplier = 1; // external link bw multiplier of the global bandwidth + + nodes[0] = chip+m_nodes*2+RubyConfig::numberOfChips(); + nodes[1] = other_chip+m_nodes*2+RubyConfig::numberOfChips(); + + // insert link + nodePairs.insertAtBottom(nodes); + latencies.insertAtBottom(latency); + bw_multis.insertAtBottom(bw_multiplier); + + // opposite direction link + Vector < SwitchID > otherDirectionNodes; + otherDirectionNodes.setSize(2); + otherDirectionNodes[0] = nodes[1]; + otherDirectionNodes[1] = nodes[0]; + nodePairs.insertAtBottom(otherDirectionNodes); + latencies.insertAtBottom(latency); + bw_multis.insertAtBottom(bw_multiplier); + } + } + + // add links + ASSERT(nodePairs.size() == latencies.size() && latencies.size() == bw_multis.size()) + for (int k = 0; k < nodePairs.size(); k++) { + ASSERT(nodePairs[k].size() == 2); + addLink(nodePairs[k][0], nodePairs[k][1], latencies[k], bw_multis[k]); + } +} + +// make a network as described by the networkFile +void Topology::makeFileSpecified() +{ + + Vector< Vector < SwitchID > > nodePairs; // node pairs extracted from the file + Vector<int> latencies; // link latencies for each link extracted + Vector<int> bw_multis; // bw multipliers for each link extracted + Vector<int> weights; // link weights used to enfore e-cube deadlock free routing + Vector< SwitchID > int_network_switches; // internal switches extracted from the file + Vector<bool> endpointConnectionExist; // used to ensure all endpoints are connected to the network + + endpointConnectionExist.setSize(m_nodes); + + // initialize endpoint check vector + for (int k = 0; k < endpointConnectionExist.size(); k++) { + endpointConnectionExist[k] = false; + } + + string filename = "network/simple/Network_Files/"; + filename = filename+g_CACHE_DESIGN + +"_Procs-"+int_to_string(RubyConfig::numberOfProcessors()) + +"_ProcsPerChip-"+int_to_string(RubyConfig::numberOfProcsPerChip()) + +"_L2Banks-"+int_to_string(RubyConfig::numberOfL2Cache()) + +"_Memories-"+int_to_string(RubyConfig::numberOfMemories()) + +".txt"; + + if (g_SIMICS) { + filename = "../../../ruby/"+filename; + } + ifstream networkFile( filename.c_str() , ios::in); + if (!networkFile.is_open()) { + cerr << "Error: Could not open network file: " << filename << endl; + cerr << "Probably no network file exists for " << RubyConfig::numberOfProcessors() + << " processors and " << RubyConfig::numberOfProcsPerChip() << " procs per chip " << endl; + exit(1); + } + + string line = ""; + + while (!networkFile.eof()) { + + Vector < SwitchID > nodes; + nodes.setSize(2); + int latency = -1; // null latency + int weight = -1; // null weight + int bw_multiplier = DEFAULT_BW_MULTIPLIER; // default multiplier incase the network file doesn't define it + int i = 0; // node pair index + int varsFound = 0; // number of varsFound on the line + int internalNodes = 0; // used to determine if the link is between 2 internal nodes + std::getline(networkFile, line, '\n'); + string varStr = string_split(line, ' '); + + // parse the current line in the file + while (varStr != "") { + string label = string_split(varStr, ':'); + + // valid node labels + if (label == "ext_node" || label == "int_node") { + ASSERT(i < 2); // one link between 2 switches per line + varsFound++; + bool isNewIntSwitch = true; + if (label == "ext_node") { // input link to node + MachineType machine = string_to_MachineType(string_split(varStr, ':')); + string nodeStr = string_split(varStr, ':'); + if (string_split(varStr, ':') == "bank") { + nodes[i] = MachineType_base_number(machine) + + atoi(nodeStr.c_str()) + + atoi((string_split(varStr, ':')).c_str())*RubyConfig::numberOfChips(); + } else { + nodes[i] = MachineType_base_number(machine) + + atoi(nodeStr.c_str()); + } + // in nodes should be numbered 0 to m_nodes-1 + ASSERT(nodes[i] >= 0 && nodes[i] < m_nodes); + isNewIntSwitch = false; + endpointConnectionExist[nodes[i]] = true; + } + if (label == "int_node") { // interior node + nodes[i] = atoi((string_split(varStr, ':')).c_str())+m_nodes*2; + // in nodes should be numbered >= m_nodes*2 + ASSERT(nodes[i] >= m_nodes*2); + for (int k = 0; k < int_network_switches.size(); k++) { + if (int_network_switches[k] == nodes[i]) { + isNewIntSwitch = false; + } + } + if (isNewIntSwitch) { // if internal switch + m_number_of_switches++; + int_network_switches.insertAtBottom(nodes[i]); + } + internalNodes++; + } + i++; + } else if (label == "link_latency") { + latency = atoi((string_split(varStr, ':')).c_str()); + varsFound++; + } else if (label == "bw_multiplier") { // not necessary, defaults to DEFAULT_BW_MULTIPLIER + bw_multiplier = atoi((string_split(varStr, ':')).c_str()); + } else if (label == "link_weight") { // not necessary, defaults to link_latency + weight = atoi((string_split(varStr, ':')).c_str()); + } else if (label == "processors") { + ASSERT(atoi((string_split(varStr, ':')).c_str()) == RubyConfig::numberOfProcessors()); + } else if (label == "bw_unit") { + ASSERT(atoi((string_split(varStr, ':')).c_str()) == g_endpoint_bandwidth); + } else if (label == "procs_per_chip") { + ASSERT(atoi((string_split(varStr, ':')).c_str()) == RubyConfig::numberOfProcsPerChip()); + } else if (label == "L2banks") { + ASSERT(atoi((string_split(varStr, ':')).c_str()) == RubyConfig::numberOfL2Cache()); + } else if (label == "memories") { + ASSERT(atoi((string_split(varStr, ':')).c_str()) == RubyConfig::numberOfMemories()); + } else { + cerr << "Error: Unexpected Identifier: " << label << endl; + exit(1); + } + varStr = string_split(line, ' '); + } + if (varsFound == 3) { // all three necessary link variables where found so add the link + nodePairs.insertAtBottom(nodes); + latencies.insertAtBottom(latency); + if (weight != -1) { + weights.insertAtBottom(weight); + } else { + weights.insertAtBottom(latency); + } + bw_multis.insertAtBottom(bw_multiplier); + Vector < SwitchID > otherDirectionNodes; + otherDirectionNodes.setSize(2); + otherDirectionNodes[0] = nodes[1]; + if (internalNodes == 2) { // this is an internal link + otherDirectionNodes[1] = nodes[0]; + } else { + otherDirectionNodes[1] = nodes[0]+m_nodes; + } + nodePairs.insertAtBottom(otherDirectionNodes); + latencies.insertAtBottom(latency); + if (weight != -1) { + weights.insertAtBottom(weight); + } else { + weights.insertAtBottom(latency); + } + bw_multis.insertAtBottom(bw_multiplier); + } else { + if (varsFound != 0) { // if this is not a valid link, then no vars should have been found + cerr << "Error in line: " << line << endl; + exit(1); + } + } + } // end of file + + // makes sure all enpoints are connected in the soon to be created network + for (int k = 0; k < endpointConnectionExist.size(); k++) { + if (endpointConnectionExist[k] == false) { + cerr << "Error: Unconnected Endpoint: " << k << endl; + exit(1); + } + } + + ASSERT(nodePairs.size() == latencies.size() && latencies.size() == bw_multis.size() && latencies.size() == weights.size()) + for (int k = 0; k < nodePairs.size(); k++) { + ASSERT(nodePairs[k].size() == 2); + addLink(nodePairs[k][0], nodePairs[k][1], latencies[k], bw_multis[k], weights[k]); + } + + networkFile.close(); +} + +void Topology::createLinks(bool isReconfiguration) +{ + // Find maximum switchID + + SwitchID max_switch_id = 0; + for (int i=0; i<m_links_src_vector.size(); i++) { + max_switch_id = max(max_switch_id, m_links_src_vector[i]); + max_switch_id = max(max_switch_id, m_links_dest_vector[i]); + } + + // Initialize weight vector + Matrix topology_weights; + Matrix topology_latency; + Matrix topology_bw_multis; + int num_switches = max_switch_id+1; + topology_weights.setSize(num_switches); + topology_latency.setSize(num_switches); + topology_bw_multis.setSize(num_switches); + m_component_latencies.setSize(num_switches); // FIXME setting the size of a member variable here is a HACK! + m_component_inter_switches.setSize(num_switches); // FIXME setting the size of a member variable here is a HACK! + for(int i=0; i<topology_weights.size(); i++) { + topology_weights[i].setSize(num_switches); + topology_latency[i].setSize(num_switches); + topology_bw_multis[i].setSize(num_switches); + m_component_latencies[i].setSize(num_switches); + m_component_inter_switches[i].setSize(num_switches); // FIXME setting the size of a member variable here is a HACK! + for(int j=0; j<topology_weights[i].size(); j++) { + topology_weights[i][j] = INFINITE_LATENCY; + topology_latency[i][j] = -1; // initialize to an invalid value + topology_bw_multis[i][j] = -1; // initialize to an invalid value + m_component_latencies[i][j] = -1; // initialize to an invalid value + m_component_inter_switches[i][j] = 0; // initially assume direct connections / no intermediate switches between components + } + } + + // Set identity weights to zero + for(int i=0; i<topology_weights.size(); i++) { + topology_weights[i][i] = 0; + } + + // Fill in the topology weights and bandwidth multipliers + for (int i=0; i<m_links_src_vector.size(); i++) { + topology_weights[m_links_src_vector[i]][m_links_dest_vector[i]] = m_links_weight_vector[i]; + topology_latency[m_links_src_vector[i]][m_links_dest_vector[i]] = m_links_latency_vector[i]; + m_component_latencies[m_links_src_vector[i]][m_links_dest_vector[i]] = m_links_latency_vector[i]; // initialize to latency vector + topology_bw_multis[m_links_src_vector[i]][m_links_dest_vector[i]] = m_bw_multiplier_vector[i]; + } + + // Walk topology and hookup the links + Matrix dist = shortest_path(topology_weights, m_component_latencies, m_component_inter_switches); + for(int i=0; i<topology_weights.size(); i++) { + for(int j=0; j<topology_weights[i].size(); j++) { + int weight = topology_weights[i][j]; + int bw_multiplier = topology_bw_multis[i][j]; + int latency = topology_latency[i][j]; + if (weight > 0 && weight != INFINITE_LATENCY) { + NetDest destination_set = shortest_path_to_node(i, j, topology_weights, dist); + assert(latency != -1); + makeLink(i, j, destination_set, latency, weight, bw_multiplier, isReconfiguration); + } + } + } +} + +SwitchID Topology::newSwitchID() +{ + m_number_of_switches++; + return m_number_of_switches-1+m_nodes+m_nodes; +} + +void Topology::addLink(SwitchID src, SwitchID dest, int link_latency) +{ + addLink(src, dest, link_latency, DEFAULT_BW_MULTIPLIER, link_latency); +} + +void Topology::addLink(SwitchID src, SwitchID dest, int link_latency, int bw_multiplier) +{ + addLink(src, dest, link_latency, bw_multiplier, link_latency); +} + +void Topology::addLink(SwitchID src, SwitchID dest, int link_latency, int bw_multiplier, int link_weight) +{ + ASSERT(src <= m_number_of_switches+m_nodes+m_nodes); + ASSERT(dest <= m_number_of_switches+m_nodes+m_nodes); + m_links_src_vector.insertAtBottom(src); + m_links_dest_vector.insertAtBottom(dest); + m_links_latency_vector.insertAtBottom(link_latency); + m_links_weight_vector.insertAtBottom(link_weight); + m_bw_multiplier_vector.insertAtBottom(bw_multiplier); +} + +void Topology::makeLink(SwitchID src, SwitchID dest, const NetDest& routing_table_entry, int link_latency, int link_weight, int bw_multiplier, bool isReconfiguration) +{ + // Make sure we're not trying to connect two end-point nodes directly together + assert((src >= 2*m_nodes) || (dest >= 2*m_nodes)); + + if (src < m_nodes) { + m_network_ptr->makeInLink(src, dest-(2*m_nodes), routing_table_entry, link_latency, bw_multiplier, isReconfiguration); + } else if (dest < 2*m_nodes) { + assert(dest >= m_nodes); + NodeID node = dest-m_nodes; + m_network_ptr->makeOutLink(src-(2*m_nodes), node, routing_table_entry, link_latency, link_weight, bw_multiplier, isReconfiguration); + } else { + assert((src >= 2*m_nodes) && (dest >= 2*m_nodes)); + m_network_ptr->makeInternalLink(src-(2*m_nodes), dest-(2*m_nodes), routing_table_entry, link_latency, link_weight, bw_multiplier, isReconfiguration); + } +} + +void Topology::printConfig(ostream& out) const +{ + assert(m_component_latencies.size() > 0); + + out << "--- Begin Topology Print ---" << endl; + out << endl; + out << "Topology print ONLY indicates the _NETWORK_ latency between two machines" << endl; + out << "It does NOT include the latency within the machines" << endl; + out << endl; + for (int m=0; m<MachineType_NUM; m++) { + for (int i=0; i<MachineType_base_count((MachineType)m); i++) { + MachineID cur_mach = {(MachineType)m, i}; + out << cur_mach << " Network Latencies" << endl; + for (int n=0; n<MachineType_NUM; n++) { + for (int j=0; j<MachineType_base_count((MachineType)n); j++) { + MachineID dest_mach = {(MachineType)n, j}; + if (cur_mach != dest_mach) { + int link_latency = m_component_latencies[MachineType_base_number((MachineType)m)+i][MachineType_base_number(MachineType_NUM)+MachineType_base_number((MachineType)n)+j]; + int intermediate_switches = m_component_inter_switches[MachineType_base_number((MachineType)m)+i][MachineType_base_number(MachineType_NUM)+MachineType_base_number((MachineType)n)+j]; + out << " " << cur_mach << " -> " << dest_mach << " net_lat: " + << link_latency+intermediate_switches << endl; // NOTE switches are assumed to have single cycle latency + } + } + } + out << endl; + } + } + + out << "--- End Topology Print ---" << endl; +} + +/**************************************************************************/ + +// The following all-pairs shortest path algorithm is based on the +// discussion from Cormen et al., Chapter 26.1. + +static void extend_shortest_path(Matrix& current_dist, Matrix& latencies, Matrix& inter_switches) +{ + bool change = true; + int nodes = current_dist.size(); + + while (change) { + change = false; + for (int i=0; i<nodes; i++) { + for (int j=0; j<nodes; j++) { + int minimum = current_dist[i][j]; + int previous_minimum = minimum; + int intermediate_switch = -1; + for (int k=0; k<nodes; k++) { + minimum = min(minimum, current_dist[i][k] + current_dist[k][j]); + if (previous_minimum != minimum) { + intermediate_switch = k; + inter_switches[i][j] = inter_switches[i][k] + inter_switches[k][j] + 1; + } + previous_minimum = minimum; + } + if (current_dist[i][j] != minimum) { + change = true; + current_dist[i][j] = minimum; + assert(intermediate_switch >= 0); + assert(intermediate_switch < latencies[i].size()); + latencies[i][j] = latencies[i][intermediate_switch] + latencies[intermediate_switch][j]; + } + } + } + } +} + +static Matrix shortest_path(const Matrix& weights, Matrix& latencies, Matrix& inter_switches) +{ + Matrix dist = weights; + extend_shortest_path(dist, latencies, inter_switches); + return dist; +} + +static bool link_is_shortest_path_to_node(SwitchID src, SwitchID next, SwitchID final, + const Matrix& weights, const Matrix& dist) +{ + return (weights[src][next] + dist[next][final] == dist[src][final]); +} + +static NetDest shortest_path_to_node(SwitchID src, SwitchID next, + const Matrix& weights, const Matrix& dist) +{ + NetDest result; + int d = 0; + int machines; + int max_machines; + + machines = MachineType_NUM; + max_machines = MachineType_base_number(MachineType_NUM); + + for (int m=0; m<machines; m++) { + for (int i=0; i<MachineType_base_count((MachineType)m); i++) { + // we use "d+max_machines" below since the "destination" switches for the machines are numbered + // [MachineType_base_number(MachineType_NUM)...2*MachineType_base_number(MachineType_NUM)-1] + // for the component network + if (link_is_shortest_path_to_node(src, next, + d+max_machines, + weights, dist)) { + MachineID mach = {(MachineType)m, i}; + result.add(mach); + } + d++; + } + } + + DEBUG_MSG(NETWORK_COMP, MedPrio, "returning shortest path"); + DEBUG_EXPR(NETWORK_COMP, MedPrio, (src-(2*max_machines))); + DEBUG_EXPR(NETWORK_COMP, MedPrio, (next-(2*max_machines))); + DEBUG_EXPR(NETWORK_COMP, MedPrio, src); + DEBUG_EXPR(NETWORK_COMP, MedPrio, next); + DEBUG_EXPR(NETWORK_COMP, MedPrio, result); + DEBUG_NEWLINE(NETWORK_COMP, MedPrio); + + return result; +} + diff --git a/src/mem/ruby/network/simple/Topology.hh b/src/mem/ruby/network/simple/Topology.hh new file mode 100644 index 000000000..bfc503087 --- /dev/null +++ b/src/mem/ruby/network/simple/Topology.hh @@ -0,0 +1,126 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Topology.h + * + * Description: The topology here is configurable; it can be a hierachical + * (default one) or a 2D torus or a 2D torus with half switches + * killed. I think all input port has a + * one-input-one-output switch connected just to control and + * bandwidth, since we don't control bandwidth on input ports. + * Basically, the class has a vector of nodes and edges. First + * 2*m_nodes elements in the node vector are input and output + * ports. Edges are represented in two vectors of src and dest + * nodes. All edges have latency. + * + * $Id$ + * + * */ + +#ifndef TOPOLOGY_H +#define TOPOLOGY_H + +#include "Global.hh" +#include "Vector.hh" +#include "NodeID.hh" + +class Network; +class NetDest; + +typedef Vector < Vector <int> > Matrix; + +class Topology { +public: + // Constructors + Topology(Network* network_ptr, int number_of_nodes); + + // Destructor + ~Topology() {} + + // Public Methods + int numSwitches() const { return m_number_of_switches; } + void createLinks(bool isReconfiguration); + + void printStats(ostream& out) const {} + void clearStats() {} + void printConfig(ostream& out) const; + void print(ostream& out) const { out << "[Topology]"; } + +private: + // Private Methods + void init(); + SwitchID newSwitchID(); + void addLink(SwitchID src, SwitchID dest, int link_latency); + void addLink(SwitchID src, SwitchID dest, int link_latency, int bw_multiplier); + void addLink(SwitchID src, SwitchID dest, int link_latency, int bw_multiplier, int link_weight); + void makeLink(SwitchID src, SwitchID dest, const NetDest& routing_table_entry, int link_latency, int weight, int bw_multiplier, bool isReconfiguration); + + void makeHierarchicalSwitch(int fan_out_degree); + void make2DTorus(); + void makePtToPt(); + void makeFileSpecified(); + + void makeSwitchesPerChip(Vector< Vector < SwitchID > > &nodePairs, Vector<int> &latencies, Vector<int> &bw_multis, int numberOfChips); + + string getDesignStr(); + // Private copy constructor and assignment operator + Topology(const Topology& obj); + Topology& operator=(const Topology& obj); + + // Data Members (m_ prefix) + Network* m_network_ptr; + NodeID m_nodes; + int m_number_of_switches; + + Vector<SwitchID> m_links_src_vector; + Vector<SwitchID> m_links_dest_vector; + Vector<int> m_links_latency_vector; + Vector<int> m_links_weight_vector; + Vector<int> m_bw_multiplier_vector; + + Matrix m_component_latencies; + Matrix m_component_inter_switches; +}; + +// Output operator declaration +ostream& operator<<(ostream& out, const Topology& obj); + +// ******************* Definitions ******************* + +// Output operator definition +extern inline +ostream& operator<<(ostream& out, const Topology& obj) +{ + obj.print(out); + out << flush; + return out; +} + +#endif |