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Diffstat (limited to 'src/mem/ruby/profiler/Profiler.cc')
-rw-r--r--src/mem/ruby/profiler/Profiler.cc82
1 files changed, 3 insertions, 79 deletions
diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc
index 51e3e8398..e8aa7edf9 100644
--- a/src/mem/ruby/profiler/Profiler.cc
+++ b/src/mem/ruby/profiler/Profiler.cc
@@ -380,9 +380,9 @@ void Profiler::printStats(ostream& out, bool short_stats)
out << endl;
- m_L1D_cache_profiler_ptr->printStats(out);
- m_L1I_cache_profiler_ptr->printStats(out);
- m_L2_cache_profiler_ptr->printStats(out);
+ // m_L1D_cache_profiler_ptr->printStats(out);
+ // m_L1I_cache_profiler_ptr->printStats(out);
+ // m_L2_cache_profiler_ptr->printStats(out);
out << endl;
@@ -773,25 +773,6 @@ void Profiler::clearStats()
m_ruby_start = g_eventQueue_ptr->getTime();
}
-void Profiler::addPrimaryStatSample(const CacheMsg& msg, NodeID id)
-{
- if (Protocol::m_TwoLevelCache) {
- if (msg.getType() == CacheRequestType_IFETCH) {
- addL1IStatSample(msg, id);
- } else {
- addL1DStatSample(msg, id);
- }
- // profile the address after an L1 miss (outside of the processor for CMP)
- if (Protocol::m_CMP) {
- addAddressTraceSample(msg, id);
- }
- } else {
- addL2StatSample(CacheRequestType_to_GenericRequestType(msg.getType()),
- msg.getAccessMode(), msg.getSize(), msg.getPrefetch(), id);
- addAddressTraceSample(msg, id);
- }
-}
-
void Profiler::profileConflictingRequests(const Address& addr)
{
assert(addr == line_address(addr));
@@ -805,39 +786,6 @@ void Profiler::profileConflictingRequests(const Address& addr)
m_conflicting_map_ptr->add(addr, current_time);
}
-void Profiler::addSecondaryStatSample(CacheRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id)
-{
- addSecondaryStatSample(CacheRequestType_to_GenericRequestType(requestType), type, msgSize, pfBit, id);
-}
-
-void Profiler::addSecondaryStatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id)
-{
- addL2StatSample(requestType, type, msgSize, pfBit, id);
-}
-
-void Profiler::addL2StatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id)
-{
- m_perProcTotalMisses[id]++;
- if (type == AccessModeType_SupervisorMode) {
- m_perProcSupervisorMisses[id]++;
- } else {
- m_perProcUserMisses[id]++;
- }
- m_L2_cache_profiler_ptr->addStatSample(requestType, type, msgSize, pfBit);
-}
-
-void Profiler::addL1DStatSample(const CacheMsg& msg, NodeID id)
-{
- m_L1D_cache_profiler_ptr->addStatSample(CacheRequestType_to_GenericRequestType(msg.getType()),
- msg.getAccessMode(), msg.getSize(), msg.getPrefetch());
-}
-
-void Profiler::addL1IStatSample(const CacheMsg& msg, NodeID id)
-{
- m_L1I_cache_profiler_ptr->addStatSample(CacheRequestType_to_GenericRequestType(msg.getType()),
- msg.getAccessMode(), msg.getSize(), msg.getPrefetch());
-}
-
void Profiler::addAddressTraceSample(const CacheMsg& msg, NodeID id)
{
if (msg.getType() != CacheRequestType_IFETCH) {
@@ -1055,30 +1003,6 @@ int64 Profiler::getTotalTransactionsExecuted() const
}
-// The following case statement converts CacheRequestTypes to GenericRequestTypes
-// allowing all profiling to be done with a single enum type instead of slow strings
-GenericRequestType Profiler::CacheRequestType_to_GenericRequestType(const CacheRequestType& type) {
- switch (type) {
- case CacheRequestType_LD:
- return GenericRequestType_LD;
- break;
- case CacheRequestType_ST:
- return GenericRequestType_ST;
- break;
- case CacheRequestType_ATOMIC:
- return GenericRequestType_ATOMIC;
- break;
- case CacheRequestType_IFETCH:
- return GenericRequestType_IFETCH;
- break;
- case CacheRequestType_NULL:
- return GenericRequestType_NULL;
- break;
- default:
- ERROR_MSG("Unexpected cache request type");
- }
-}
-
void Profiler::rubyWatch(int id){
//int rn_g1 = 0;//SIMICS_get_register_number(id, "g1");
uint64 tr = 0;//SIMICS_read_register(id, rn_g1);