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-rw-r--r--src/mem/ruby/profiler/AccessTraceForAddress.cc4
-rw-r--r--src/mem/ruby/profiler/AccessTraceForAddress.hh4
-rw-r--r--src/mem/ruby/profiler/AddressProfiler.cc6
-rw-r--r--src/mem/ruby/profiler/AddressProfiler.hh2
-rw-r--r--src/mem/ruby/profiler/CacheProfiler.cc12
-rw-r--r--src/mem/ruby/profiler/CacheProfiler.hh10
-rw-r--r--src/mem/ruby/profiler/Profiler.hh2
7 files changed, 20 insertions, 20 deletions
diff --git a/src/mem/ruby/profiler/AccessTraceForAddress.cc b/src/mem/ruby/profiler/AccessTraceForAddress.cc
index e7aaa2515..9cbf71163 100644
--- a/src/mem/ruby/profiler/AccessTraceForAddress.cc
+++ b/src/mem/ruby/profiler/AccessTraceForAddress.cc
@@ -59,7 +59,7 @@ AccessTraceForAddress::print(std::ostream& out) const
void
AccessTraceForAddress::update(CacheRequestType type,
- AccessModeType access_mode, NodeID cpu,
+ RubyAccessMode access_mode, NodeID cpu,
bool sharing_miss)
{
m_touched_by.add(cpu);
@@ -74,7 +74,7 @@ AccessTraceForAddress::update(CacheRequestType type,
// ERROR_MSG("Trying to add invalid access to trace");
}
- if (access_mode == AccessModeType_UserMode) {
+ if (access_mode == RubyAccessMode_User) {
m_user++;
}
diff --git a/src/mem/ruby/profiler/AccessTraceForAddress.hh b/src/mem/ruby/profiler/AccessTraceForAddress.hh
index b950f2be2..9b6db2376 100644
--- a/src/mem/ruby/profiler/AccessTraceForAddress.hh
+++ b/src/mem/ruby/profiler/AccessTraceForAddress.hh
@@ -31,7 +31,7 @@
#include <iostream>
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
@@ -50,7 +50,7 @@ class AccessTraceForAddress
~AccessTraceForAddress();
void setAddress(const Address& addr) { m_addr = addr; }
- void update(CacheRequestType type, AccessModeType access_mode, NodeID cpu,
+ void update(CacheRequestType type, RubyAccessMode access_mode, NodeID cpu,
bool sharing_miss);
int getTotal() const;
int getSharing() const { return m_sharing; }
diff --git a/src/mem/ruby/profiler/AddressProfiler.cc b/src/mem/ruby/profiler/AddressProfiler.cc
index 5c1b7352c..6ec0e20ba 100644
--- a/src/mem/ruby/profiler/AddressProfiler.cc
+++ b/src/mem/ruby/profiler/AddressProfiler.cc
@@ -257,7 +257,7 @@ AddressProfiler::profileGetX(const Address& datablock, const Address& PC,
m_getx_sharing_histogram.add(num_indirections);
bool indirection_miss = (num_indirections > 0);
- addTraceSample(datablock, PC, CacheRequestType_ST, AccessModeType(0),
+ addTraceSample(datablock, PC, CacheRequestType_ST, RubyAccessMode(0),
requestor, indirection_miss);
}
@@ -274,14 +274,14 @@ AddressProfiler::profileGetS(const Address& datablock, const Address& PC,
m_gets_sharing_histogram.add(num_indirections);
bool indirection_miss = (num_indirections > 0);
- addTraceSample(datablock, PC, CacheRequestType_LD, AccessModeType(0),
+ addTraceSample(datablock, PC, CacheRequestType_LD, RubyAccessMode(0),
requestor, indirection_miss);
}
void
AddressProfiler::addTraceSample(Address data_addr, Address pc_addr,
CacheRequestType type,
- AccessModeType access_mode, NodeID id,
+ RubyAccessMode access_mode, NodeID id,
bool sharing_miss)
{
if (m_all_instructions) {
diff --git a/src/mem/ruby/profiler/AddressProfiler.hh b/src/mem/ruby/profiler/AddressProfiler.hh
index 5422fe095..fe822c116 100644
--- a/src/mem/ruby/profiler/AddressProfiler.hh
+++ b/src/mem/ruby/profiler/AddressProfiler.hh
@@ -55,7 +55,7 @@ class AddressProfiler
void clearStats();
void addTraceSample(Address data_addr, Address pc_addr,
- CacheRequestType type, AccessModeType access_mode,
+ CacheRequestType type, RubyAccessMode access_mode,
NodeID id, bool sharing_miss);
void profileRetry(const Address& data_addr, AccessType type, int count);
void profileGetX(const Address& datablock, const Address& PC,
diff --git a/src/mem/ruby/profiler/CacheProfiler.cc b/src/mem/ruby/profiler/CacheProfiler.cc
index a969b9074..fcad227fb 100644
--- a/src/mem/ruby/profiler/CacheProfiler.cc
+++ b/src/mem/ruby/profiler/CacheProfiler.cc
@@ -94,10 +94,10 @@ CacheProfiler::printStats(ostream& out) const
out << endl;
- for (int i = 0; i < AccessModeType_NUM; i++){
+ for (int i = 0; i < RubyAccessMode_NUM; i++){
if (m_accessModeTypeHistogram[i] > 0) {
out << description << "_access_mode_type_"
- << (AccessModeType) i << ": "
+ << (RubyAccessMode) i << ": "
<< m_accessModeTypeHistogram[i] << " "
<< 100.0 * m_accessModeTypeHistogram[i] / requests
<< "%" << endl;
@@ -122,14 +122,14 @@ CacheProfiler::clearStats()
m_prefetches = 0;
m_sw_prefetches = 0;
m_hw_prefetches = 0;
- for (int i = 0; i < AccessModeType_NUM; i++) {
+ for (int i = 0; i < RubyAccessMode_NUM; i++) {
m_accessModeTypeHistogram[i] = 0;
}
}
void
CacheProfiler::addCacheStatSample(CacheRequestType requestType,
- AccessModeType accessType,
+ RubyAccessMode accessType,
PrefetchBit pfBit)
{
m_cacheRequestType[requestType]++;
@@ -138,7 +138,7 @@ CacheProfiler::addCacheStatSample(CacheRequestType requestType,
void
CacheProfiler::addGenericStatSample(GenericRequestType requestType,
- AccessModeType accessType,
+ RubyAccessMode accessType,
PrefetchBit pfBit)
{
m_genericRequestType[requestType]++;
@@ -146,7 +146,7 @@ CacheProfiler::addGenericStatSample(GenericRequestType requestType,
}
void
-CacheProfiler::addStatSample(AccessModeType accessType,
+CacheProfiler::addStatSample(RubyAccessMode accessType,
PrefetchBit pfBit)
{
m_misses++;
diff --git a/src/mem/ruby/profiler/CacheProfiler.hh b/src/mem/ruby/profiler/CacheProfiler.hh
index 2e59c9d82..9a8fdefb4 100644
--- a/src/mem/ruby/profiler/CacheProfiler.hh
+++ b/src/mem/ruby/profiler/CacheProfiler.hh
@@ -33,7 +33,7 @@
#include <string>
#include <vector>
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/GenericRequestType.hh"
#include "mem/protocol/PrefetchBit.hh"
@@ -51,11 +51,11 @@ class CacheProfiler
void clearStats();
void addCacheStatSample(CacheRequestType requestType,
- AccessModeType type,
+ RubyAccessMode type,
PrefetchBit pfBit);
void addGenericStatSample(GenericRequestType requestType,
- AccessModeType type,
+ RubyAccessMode type,
PrefetchBit pfBit);
void print(std::ostream& out) const;
@@ -64,7 +64,7 @@ class CacheProfiler
// Private copy constructor and assignment operator
CacheProfiler(const CacheProfiler& obj);
CacheProfiler& operator=(const CacheProfiler& obj);
- void addStatSample(AccessModeType type, PrefetchBit pfBit);
+ void addStatSample(RubyAccessMode type, PrefetchBit pfBit);
std::string m_description;
int64 m_misses;
@@ -72,7 +72,7 @@ class CacheProfiler
int64 m_prefetches;
int64 m_sw_prefetches;
int64 m_hw_prefetches;
- int64 m_accessModeTypeHistogram[AccessModeType_NUM];
+ int64 m_accessModeTypeHistogram[RubyAccessMode_NUM];
std::vector<int> m_cacheRequestType;
std::vector<int> m_genericRequestType;
diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh
index c0cee1d7d..a3eb8cd71 100644
--- a/src/mem/ruby/profiler/Profiler.hh
+++ b/src/mem/ruby/profiler/Profiler.hh
@@ -51,7 +51,7 @@
#include <vector>
#include "base/hashmap.hh"
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
#include "mem/protocol/AccessType.hh"
#include "mem/protocol/CacheRequestType.hh"
#include "mem/protocol/GenericMachineType.hh"
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-08 16:29:32 +0000