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-rw-r--r--src/mem/ruby/protocol/Garnet_standalone-dir.sm2
-rw-r--r--src/mem/ruby/protocol/MESI_Two_Level-dir.sm2
-rw-r--r--src/mem/ruby/protocol/MI_example-dir.sm20
-rw-r--r--src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm2
-rw-r--r--src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm2
-rw-r--r--src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm2
-rw-r--r--src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm2
-rw-r--r--src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm2
-rw-r--r--src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm10
-rw-r--r--src/mem/ruby/protocol/MOESI_CMP_token-dir.sm8
-rw-r--r--src/mem/ruby/protocol/MOESI_hammer-dir.sm2
-rw-r--r--src/mem/ruby/protocol/RubySlicc_Types.sm10
12 files changed, 30 insertions, 34 deletions
diff --git a/src/mem/ruby/protocol/Garnet_standalone-dir.sm b/src/mem/ruby/protocol/Garnet_standalone-dir.sm
index 3a4327972..663ba1703 100644
--- a/src/mem/ruby/protocol/Garnet_standalone-dir.sm
+++ b/src/mem/ruby/protocol/Garnet_standalone-dir.sm
@@ -55,7 +55,7 @@ machine(MachineType:Directory, "Garnet_standalone Directory")
// TYPES
// DirectoryEntry
- structure(Entry, desc="...", interface="AbstractEntry") {
+ structure(Entry, desc="...", interface="AbstractCacheEntry", main="false") {
State DirectoryState, desc="Directory state";
DataBlock DataBlk, desc="data for the block";
}
diff --git a/src/mem/ruby/protocol/MESI_Two_Level-dir.sm b/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
index 991de5a2c..2e935de66 100644
--- a/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
+++ b/src/mem/ruby/protocol/MESI_Two_Level-dir.sm
@@ -72,7 +72,7 @@ machine(MachineType:Directory, "MESI Two Level directory protocol")
// TYPES
// DirectoryEntry
- structure(Entry, desc="...", interface="AbstractEntry") {
+ structure(Entry, desc="...", interface="AbstractCacheEntry", main="false") {
State DirectoryState, desc="Directory state";
MachineID Owner;
}
diff --git a/src/mem/ruby/protocol/MI_example-dir.sm b/src/mem/ruby/protocol/MI_example-dir.sm
index e9f652152..471608de0 100644
--- a/src/mem/ruby/protocol/MI_example-dir.sm
+++ b/src/mem/ruby/protocol/MI_example-dir.sm
@@ -27,7 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(MachineType:Directory, "Directory protocol")
+machine(MachineType:Directory, "Directory protocol")
: DirectoryMemory * directory;
Cycles directory_latency := 12;
Cycles to_memory_controller_latency := 1;
@@ -54,7 +54,7 @@ machine(MachineType:Directory, "Directory protocol")
M_DRD, AccessPermission:Busy, desc="Blocked on an invalidation for a DMA read";
M_DWR, AccessPermission:Busy, desc="Blocked on an invalidation for a DMA write";
- M_DWRI, AccessPermission:Busy, desc="Intermediate state M_DWR-->I";
+ M_DWRI, AccessPermission:Busy, desc="Intermediate state M_DWR-->I";
M_DRDI, AccessPermission:Busy, desc="Intermediate state M_DRD-->I";
IM, AccessPermission:Busy, desc="Intermediate state I-->M";
@@ -83,7 +83,7 @@ machine(MachineType:Directory, "Directory protocol")
// TYPES
// DirectoryEntry
- structure(Entry, desc="...", interface="AbstractEntry") {
+ structure(Entry, desc="...", interface="AbstractCacheEntry", main="false") {
State DirectoryState, desc="Directory state";
NetDest Sharers, desc="Sharers for this block";
NetDest Owner, desc="Owner of this block";
@@ -125,7 +125,7 @@ machine(MachineType:Directory, "Directory protocol")
directory.allocate(addr, new Entry));
return dir_entry;
}
-
+
State getState(TBE tbe, Addr addr) {
if (is_valid(tbe)) {
return tbe.TBEState;
@@ -150,7 +150,7 @@ machine(MachineType:Directory, "Directory protocol")
}
getDirectoryEntry(addr).DirectoryState := state;
-
+
if (state == State:I) {
assert(getDirectoryEntry(addr).Owner.count() == 0);
assert(getDirectoryEntry(addr).Sharers.count() == 0);
@@ -354,7 +354,7 @@ machine(MachineType:Directory, "Directory protocol")
out_msg.PhysicalAddress := address;
out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:ACK;
- out_msg.Destination.add(tbe.DmaRequestor);
+ out_msg.Destination.add(tbe.DmaRequestor);
out_msg.MessageSize := MessageSizeType:Writeback_Control;
}
}
@@ -401,7 +401,7 @@ machine(MachineType:Directory, "Directory protocol")
action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
dmaRequestQueue_in.dequeue(clockEdge());
}
-
+
action(v_allocateTBE, "v", desc="Allocate TBE") {
peek(dmaRequestQueue_in, DMARequestMsg) {
TBEs.allocate(address);
@@ -490,7 +490,7 @@ machine(MachineType:Directory, "Directory protocol")
transition({IM, MI, ID, ID_W}, {GETX, GETS, PUTX, PUTX_NotOwner} ) {
z_recycleRequestQueue;
}
-
+
transition({IM, MI, ID, ID_W}, {DMA_READ, DMA_WRITE} ) {
y_recycleDMARequestQueue;
}
@@ -546,7 +546,7 @@ machine(MachineType:Directory, "Directory protocol")
p_popIncomingDMARequestQueue;
}
- transition(M_DRD, PUTX, M_DRDI) {
+ transition(M_DRD, PUTX, M_DRDI) {
drp_sendDMAData;
c_clearOwner;
l_queueMemoryWBRequest;
@@ -555,7 +555,7 @@ machine(MachineType:Directory, "Directory protocol")
transition(M_DRDI, Memory_Ack, I) {
l_sendWriteBackAck;
- w_deallocateTBE;
+ w_deallocateTBE;
l_popMemQueue;
}
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
index cc5ceb0b5..152d8b50a 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-Region-dir.sm
@@ -159,7 +159,7 @@ machine(MachineType:Directory, "AMD_Base-like protocol")
// TYPES
// DirectoryEntry
- structure(Entry, desc="...", interface="AbstractEntry") {
+ structure(Entry, desc="...", interface="AbstractCacheEntry", main="false") {
State DirectoryState, desc="Directory state";
DataBlock DataBlk, desc="data for the block";
NetDest VicDirtyIgnore, desc="VicDirty coming from whom to ignore";
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
index 4cde5ad03..971b84634 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-dir.sm
@@ -119,7 +119,7 @@ machine(MachineType:Directory, "AMD Baseline protocol")
// TYPES
// DirectoryEntry
- structure(Entry, desc="...", interface="AbstractEntry") {
+ structure(Entry, desc="...", interface="AbstractCacheEntry", main="false") {
State DirectoryState, desc="Directory state";
DataBlock DataBlk, desc="data for the block";
NetDest VicDirtyIgnore, desc="VicDirty coming from whom to ignore";
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm b/src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
index d23094a2e..51efb1015 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base-probeFilter.sm
@@ -148,7 +148,7 @@ machine(MachineType:Directory, "AMD Baseline protocol")
}
// DirectoryEntry
- structure(Entry, desc="...", interface="AbstractEntry") {
+ structure(Entry, desc="...", interface="AbstractCacheEntry", main="false") {
State DirectoryState, desc="Directory state";
DataBlock DataBlk, desc="data for the block";
NetDest VicDirtyIgnore, desc="VicDirty coming from whom to ignore";
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
index f20085fd5..18e3b891e 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm
@@ -193,7 +193,7 @@ machine(MachineType:L2Cache, "Token protocol")
}
- structure(DirEntry, desc="...", interface="AbstractEntry") {
+ structure(DirEntry, desc="...", interface="AbstractCacheEntry", main="false") {
NetDest Sharers, desc="Set of the internal processors that want the block in shared state";
MachineID Owner, desc="ID of the L1 cache to forward the block to once we get a response";
bool OwnerValid, default="false", desc="true if Owner means something";
diff --git a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
index f12d16658..29f862e2e 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_directory-dir.sm
@@ -106,7 +106,7 @@ machine(MachineType:Directory, "Directory protocol")
// TYPES
// DirectoryEntry
- structure(Entry, desc="...", interface='AbstractEntry') {
+ structure(Entry, desc="...", interface='AbstractCacheEntry', main="false") {
State DirectoryState, desc="Directory state";
NetDest Sharers, desc="Sharers for this block";
NetDest Owner, desc="Owner of this block";
diff --git a/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
index 948a2d95f..119508aa8 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_token-L2cache.sm
@@ -35,7 +35,7 @@ machine(MachineType:L2Cache, "Token protocol")
// L2 BANK QUEUES
// From local bank of L2 cache TO the network
-
+
// this L2 bank -> a local L1 || mod-directory
MessageBuffer * responseFromL2Cache, network="To", virtual_network="4",
vnet_type="response";
@@ -45,10 +45,10 @@ machine(MachineType:L2Cache, "Token protocol")
// this L2 bank -> a local L1
MessageBuffer * L1RequestFromL2Cache, network="To", virtual_network="1",
vnet_type="request";
-
-
+
+
// FROM the network to this local bank of L2 cache
-
+
// a local L1 || mod-directory -> this L2 bank
MessageBuffer * responseToL2Cache, network="From", virtual_network="4",
vnet_type="response";
@@ -123,7 +123,7 @@ machine(MachineType:L2Cache, "Token protocol")
DataBlock DataBlk, desc="data for the block";
}
- structure(DirEntry, desc="...", interface="AbstractEntry") {
+ structure(DirEntry, desc="...", interface="AbstractCacheEntry", main="false") {
Set Sharers, desc="Set of the internal processors that want the block in shared state";
bool exclusive, default="false", desc="if local exclusive is likely";
}
diff --git a/src/mem/ruby/protocol/MOESI_CMP_token-dir.sm b/src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
index b9b65b585..2e3f12024 100644
--- a/src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_CMP_token-dir.sm
@@ -47,17 +47,17 @@ machine(MachineType:Directory, "Token protocol")
MessageBuffer * requestFromDir, network="To", virtual_network="1",
vnet_type="request";
-
+
// Message Queues to dir from other controllers / network
MessageBuffer * responseToDir, network="From", virtual_network="4",
vnet_type="response";
MessageBuffer * persistentToDir, network="From", virtual_network="3",
vnet_type="persistent";
-
+
MessageBuffer * requestToDir, network="From", virtual_network="2",
vnet_type="request";
-
+
MessageBuffer * dmaRequestToDir, network="From", virtual_network="0",
vnet_type="request";
@@ -120,7 +120,7 @@ machine(MachineType:Directory, "Token protocol")
// TYPES
// DirectoryEntry
- structure(Entry, desc="...", interface="AbstractEntry") {
+ structure(Entry, desc="...", interface="AbstractCacheEntry", main="false") {
State DirectoryState, desc="Directory state";
int Tokens, default="max_tokens()", desc="Number of tokens for the line we're holding";
diff --git a/src/mem/ruby/protocol/MOESI_hammer-dir.sm b/src/mem/ruby/protocol/MOESI_hammer-dir.sm
index 3b0016868..3c457b171 100644
--- a/src/mem/ruby/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/ruby/protocol/MOESI_hammer-dir.sm
@@ -148,7 +148,7 @@ machine(MachineType:Directory, "AMD Hammer-like protocol")
// TYPES
// DirectoryEntry
- structure(Entry, desc="...", interface="AbstractEntry") {
+ structure(Entry, desc="...", interface="AbstractCacheEntry", main="false") {
State DirectoryState, desc="Directory state";
}
diff --git a/src/mem/ruby/protocol/RubySlicc_Types.sm b/src/mem/ruby/protocol/RubySlicc_Types.sm
index 2d4c250da..fd7628965 100644
--- a/src/mem/ruby/protocol/RubySlicc_Types.sm
+++ b/src/mem/ruby/protocol/RubySlicc_Types.sm
@@ -174,22 +174,18 @@ structure(RubyRequest, desc="...", interface="Message", external="yes") {
PacketPtr pkt, desc="Packet associated with this request";
}
-structure(AbstractEntry, primitive="yes", external = "yes") {
+structure(AbstractCacheEntry, primitive="yes", external = "yes") {
void changePermission(AccessPermission);
}
structure (DirectoryMemory, external = "yes") {
- AbstractEntry allocate(Addr, AbstractEntry);
- AbstractEntry lookup(Addr);
+ AbstractCacheEntry allocate(Addr, AbstractCacheEntry);
+ AbstractCacheEntry lookup(Addr);
bool isPresent(Addr);
void invalidateBlock(Addr);
void recordRequestType(DirectoryRequestType);
}
-structure(AbstractCacheEntry, primitive="yes", external = "yes") {
- void changePermission(AccessPermission);
-}
-
structure (CacheMemory, external = "yes") {
bool cacheAvail(Addr);
Addr cacheProbe(Addr);
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-25 16:16:30 +0000