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-rw-r--r--src/mem/ruby/slicc_interface/Controller.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py
index dc65e7f7e..a5ad45145 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -35,6 +35,7 @@ class RubyController(SimObject):
cxx_class = 'AbstractController'
abstract = True
version = Param.Int("")
+ cntrl_id = Param.Int("")
transitions_per_cycle = \
Param.Int(32, "no. of SLICC state machine transitions per cycle")
buffer_size = Param.Int(0, "max buffer size 0 means infinite")