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-rw-r--r--src/mem/ruby/slicc_interface/Controller.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py
index f8242322e..638d50b61 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -36,7 +36,8 @@ class RubyController(ClockedObject):
cxx_header = "mem/ruby/slicc_interface/AbstractController.hh"
abstract = True
version = Param.Int("")
- cntrl_id = Param.Int("")
+ cluster_id = Param.UInt32(0, "Id of this controller's cluster")
+
transitions_per_cycle = \
Param.Int(32, "no. of SLICC state machine transitions per cycle")
buffer_size = Param.Int(0, "max buffer size 0 means infinite")