diff options
Diffstat (limited to 'src/mem/ruby/slicc_interface')
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractCacheEntry.cc | 2 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractCacheEntry.hh | 3 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractChip.cc | 47 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractChip.hh | 126 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.hh | 33 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh | 285 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc | 25 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/RubySlicc_Util.hh | 29 |
8 files changed, 103 insertions, 447 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc index 60ca412ad..83039a9b0 100644 --- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc +++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc @@ -37,6 +37,8 @@ #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" AbstractCacheEntry::AbstractCacheEntry() { + m_Address.setAddress(0); + m_Permission = AccessPermission_NotPresent; } // still need to define destructor for subclasses diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh index 18dc16ca8..be1f14b05 100644 --- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh +++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh @@ -41,6 +41,8 @@ #include "mem/ruby/common/Address.hh" #include "mem/protocol/AccessPermission.hh" +class DataBlock; + class AbstractCacheEntry { public: // Constructors @@ -53,6 +55,7 @@ public: // The methods below are those called by ruby runtime, add when it is // absolutely necessary and should all be virtual function. + virtual DataBlock& getDataBlk() = 0; virtual void print(ostream& out) const = 0; diff --git a/src/mem/ruby/slicc_interface/AbstractChip.cc b/src/mem/ruby/slicc_interface/AbstractChip.cc deleted file mode 100644 index 021c95b9d..000000000 --- a/src/mem/ruby/slicc_interface/AbstractChip.cc +++ /dev/null @@ -1,47 +0,0 @@ - -/* - * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * $Id$ - * - * Description: See AbstractChip.hh - * - */ - -#include "mem/ruby/slicc_interface/AbstractChip.hh" - -AbstractChip::AbstractChip(NodeID id, Network* net_ptr) { - m_id = id; - m_net_ptr = net_ptr; - m_L1Cache_sequencer_vec.setSize(0); -} - -// still need to be defined for subclasses -AbstractChip::~AbstractChip() { -} diff --git a/src/mem/ruby/slicc_interface/AbstractChip.hh b/src/mem/ruby/slicc_interface/AbstractChip.hh deleted file mode 100644 index d47dd6306..000000000 --- a/src/mem/ruby/slicc_interface/AbstractChip.hh +++ /dev/null @@ -1,126 +0,0 @@ - -/* - * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * $Id$ - * - * Description: Common base class for a machine chip. - * - */ - -#ifndef ABSTRACT_CHIP_H -#define ABSTRACT_CHIP_H - -#include "mem/ruby/common/Global.hh" -#include "mem/ruby/system/NodeID.hh" -#include "mem/ruby/config/RubyConfig.hh" -#include "mem/protocol/L1Cache_Entry.hh" -#include "mem/ruby/common/Address.hh" -#include "mem/gems_common/Vector.hh" - -class Network; -class Sequencer; -class StoreBuffer; -class ENTRY; -class MessageBuffer; -class CacheRecorder; -class TransactionInterfaceManager; - -template<class ENTRY> class CacheMemory; - -class AbstractChip { -public: - // Constructors - AbstractChip(NodeID chip_number, Network* net_ptr); - - // Destructor, prevent from being instantiated - virtual ~AbstractChip() = 0; - - // Public Methods - NodeID getID() const { return m_id; }; - Network* getNetwork() const { return m_net_ptr; }; - Sequencer* getSequencer(int index) const { return m_L1Cache_sequencer_vec[index]; }; - TransactionInterfaceManager* getTransactionInterfaceManager(int index) const { return m_L1Cache_xact_mgr_vec[index]; }; - void setTransactionInterfaceManager(TransactionInterfaceManager* manager, int index) { m_L1Cache_xact_mgr_vec[index] = manager; } - - // used when CHECK_COHERENCE is enabled. See RubySystem::checkGlobalCoherence() - virtual bool isBlockExclusive(const Address& addr) const { return false; } - virtual bool isBlockShared(const Address& addr) const { return false; } - - // cache dump functions - virtual void recordCacheContents(CacheRecorder& tr) const = 0; - virtual void dumpCaches(ostream& out) const = 0; - virtual void dumpCacheData(ostream& out) const = 0; - - virtual void printConfig(ostream& out) = 0; - virtual void print(ostream& out) const = 0; - - // pulic data structures - Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_L1DcacheMemory_vec; - Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_L1IcacheMemory_vec; - Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_cacheMemory_vec; - Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_L2cacheMemory_vec; - Vector < CacheMemory<L1Cache_Entry>* > m_L2Cache_L2cacheMemory_vec; - - // added so that the prefetcher and sequencer can access the L1 and L2 request queues - Vector < MessageBuffer* > m_L1Cache_optionalQueue_vec; - Vector < MessageBuffer* >m_L1Cache_mandatoryQueue_vec; - - // TSO storebuffer - Vector < StoreBuffer* > m_L1Cache_storeBuffer_vec; - - // TM transaction manager - Vector < TransactionInterfaceManager* > m_L1Cache_xact_mgr_vec; - -protected: - - // Data Members (m_ prefix) - NodeID m_id; // Chip id - Network* m_net_ptr; // Points to the Network simulator - Vector < Sequencer* > m_L1Cache_sequencer_vec; // All chip should have a sequencer - - -}; - -// Output operator declaration -ostream& operator<<(ostream& out, const AbstractChip& obj); - -// ******************* Definitions ******************* - -// Output operator definition -extern inline -ostream& operator<<(ostream& out, const AbstractChip& obj) -{ - obj.print(out); - out << flush; - return out; -} - -#endif //ABSTRACT_CHIP_H - diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh new file mode 100644 index 000000000..3a93cc745 --- /dev/null +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -0,0 +1,33 @@ + +#ifndef ABSTRACTCONTROLLER_H +#define ABSTRACTCONTROLLER_H + +#include "mem/ruby/common/Consumer.hh" +#include "mem/protocol/MachineType.hh" + +class MessageBuffer; +class Network; + +class AbstractController : public Consumer { +public: + AbstractController() {} + virtual void init(Network* net_ptr, const vector<string> & argv) = 0; + + // returns the number of controllers created of the specific subtype + // virtual int getNumberOfControllers() const = 0; + virtual MessageBuffer* getMandatoryQueue() const = 0; + virtual const int & getVersion() const = 0; + virtual const string toString() const = 0; // returns text version of controller type + virtual const string getName() const = 0; // return instance name + virtual const MachineType getMachineType() const = 0; + + virtual void print(ostream & out) const = 0; + virtual void printStats(ostream & out) const = 0; + virtual void printConfig(ostream & out) const = 0; + virtual void wakeup() = 0; + // virtual void dumpStats(ostream & out) = 0; + virtual void clearStats() = 0; + +}; + +#endif diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh index bf5778479..9ece7ae65 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh @@ -42,6 +42,7 @@ #include "mem/ruby/common/Set.hh" #include "mem/ruby/common/NetDest.hh" #include "mem/protocol/GenericMachineType.hh" +#include "mem/ruby/system/DirectoryMemory.hh" #ifdef MACHINETYPE_L1Cache #define MACHINETYPE_L1CACHE_ENUM MachineType_L1Cache @@ -61,44 +62,22 @@ #define MACHINETYPE_L3CACHE_ENUM MachineType_NUM #endif +/* #ifdef MACHINETYPE_PersistentArbiter #define MACHINETYPE_PERSISTENTARBITER_ENUM MachineType_PersistentArbiter #else #define MACHINETYPE_PERSISTENTARBITER_ENUM MachineType_NUM #endif - -#ifdef MACHINETYPE_Collector -#define MACHINETYPE_COLLECTOR_ENUM MachineType_Collector -#else -#define MACHINETYPE_COLLECTOR_ENUM MachineType_NUM -#endif - - -// used to determine the correct L1 set -// input parameters are the address and number of set bits for the L1 cache -// returns a value between 0 and the total number of L1 cache sets -inline -int map_address_to_L1CacheSet(const Address& addr, int cache_num_set_bits) -{ - return addr.bitSelect(RubyConfig::dataBlockBits(), - RubyConfig::dataBlockBits()+cache_num_set_bits-1); -} - -// used to determine the correct L2 set -// input parameters are the address and number of set bits for the L2 cache -// returns a value between 0 and the total number of L2 cache sets -inline -int map_address_to_L2CacheSet(const Address& addr, int cache_num_set_bits) +*/ +/* +inline MachineID map_Address_to_L2Cache(const Address & addr) { - assert(cache_num_set_bits == L2_CACHE_NUM_SETS_BITS); // ensure the l2 bank mapping functions agree with l2 set bits - - if (MAP_L2BANKS_TO_LOWEST_BITS) { - return addr.bitSelect(RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits(), - RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits()+cache_num_set_bits-1); - } else { - return addr.bitSelect(RubyConfig::dataBlockBits(), - RubyConfig::dataBlockBits()+cache_num_set_bits-1); - } + int L2bank = 0; + MachineID mach = {MACHINETYPE_L2CACHE_ENUM, 0}; + L2bank = addr.bitSelect(RubySystem::getBlockSizeBits(), + RubySystem::getBlockSizeBits() + RubyConfig::getNumberOfCachesPerLevel(2)-1); + mach.num = L2bank; + return mach; } // input parameter is the base ruby node of the L1 cache @@ -106,16 +85,18 @@ int map_address_to_L2CacheSet(const Address& addr, int cache_num_set_bits) inline MachineID map_L1CacheMachId_to_L2Cache(const Address& addr, MachineID L1CacheMachId) { + return map_Address_to_L2Cache(addr); + int L2bank = 0; MachineID mach = {MACHINETYPE_L2CACHE_ENUM, 0}; if (RubyConfig::L2CachePerChipBits() > 0) { - if (MAP_L2BANKS_TO_LOWEST_BITS) { - L2bank = addr.bitSelect(RubyConfig::dataBlockBits(), - RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits()-1); + if (RubyConfig::getMAP_L2BANKS_TO_LOWEST_BITS()) { + L2bank = addr.bitSelect(RubySystem::getBlockSizeBits(), + RubySystem::getBlockSizeBits()+RubyConfig::L2CachePerChipBits()-1); } else { - L2bank = addr.bitSelect(RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS, - RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS+RubyConfig::L2CachePerChipBits()-1); + L2bank = addr.bitSelect(RubySystem::getBlockSizeBits()+RubyConfig::getL2_CACHE_NUM_SETS_BITS(), + RubySystem::getBlockSizeBits()+RubyConfig::getL2_CACHE_NUM_SETS_BITS()+RubyConfig::L2CachePerChipBits()-1); } } @@ -126,72 +107,38 @@ MachineID map_L1CacheMachId_to_L2Cache(const Address& addr, MachineID L1CacheMac + L2bank; // bank # assert(mach.num < RubyConfig::numberOfL2Cache()); return mach; + } + // used to determine the correct L2 bank // input parameter is the base ruby node of the L2 cache // returns a value between 0 and total_L2_Caches_within_the_system + inline MachineID map_L2ChipId_to_L2Cache(const Address& addr, NodeID L2ChipId) { + return map_Address_to_L2Cache(addr); + assert(L2ChipId < RubyConfig::numberOfChips()); int L2bank = 0; MachineID mach = {MACHINETYPE_L2CACHE_ENUM, 0}; + L2bank = addr.bitSelect(RubySystem::getBlockSizeBits(), + RubySystem::getBlockSizeBits() + RubyConfig::numberOfCachesPerLevel(2)-1); + mach.num = L2bank; + return mach - if (RubyConfig::L2CachePerChipBits() > 0) { - if (MAP_L2BANKS_TO_LOWEST_BITS) { - L2bank = addr.bitSelect(RubyConfig::dataBlockBits(), - RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits()-1); - } else { - L2bank = addr.bitSelect(RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS, - RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS+RubyConfig::L2CachePerChipBits()-1); - } - } - - assert(L2bank < RubyConfig::numberOfL2CachePerChip()); - assert(L2bank >= 0); - - mach.num = L2ChipId*RubyConfig::numberOfL2CachePerChip() // base # - + L2bank; // bank # - assert(mach.num < RubyConfig::numberOfL2Cache()); - return mach; } + */ + // used to determine the home directory // returns a value between 0 and total_directories_within_the_system inline NodeID map_Address_to_DirectoryNode(const Address& addr) { - NodeID dirNode = 0; - - if (RubyConfig::memoryBits() > 0) { - dirNode = addr.bitSelect(RubyConfig::dataBlockBits(), - RubyConfig::dataBlockBits()+RubyConfig::memoryBits()-1); - } - - // Index indexHighPortion = address.bitSelect(MEMORY_SIZE_BITS-1, PAGE_SIZE_BITS+NUMBER_OF_MEMORY_MODULE_BITS); - // Index indexLowPortion = address.bitSelect(DATA_BLOCK_BITS, PAGE_SIZE_BITS-1); - - //Index index = indexLowPortion | (indexHighPortion << (PAGE_SIZE_BITS - DATA_BLOCK_BITS)); - -/* - -ADDRESS_WIDTH MEMORY_SIZE_BITS PAGE_SIZE_BITS DATA_BLOCK_BITS - | | | | - \ / \ / \ / \ / 0 - ----------------------------------------------------------------------- - | unused |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| | - | |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| | - ----------------------------------------------------------------------- - indexHighPortion indexLowPortion - <-------> - NUMBER_OF_MEMORY_MODULE_BITS - */ - - assert(dirNode < RubyConfig::numberOfMemories()); - assert(dirNode >= 0); - return dirNode; + return DirectoryMemory::mapAddressToDirectoryVersion(addr); } // used to determine the home directory @@ -204,29 +151,13 @@ MachineID map_Address_to_Directory(const Address &addr) } inline -MachineID map_Address_to_CentralArbiterNode(const Address& addr) -{ - MachineType t = MACHINETYPE_PERSISTENTARBITER_ENUM; - MachineID mach = {t, map_Address_to_DirectoryNode(addr)}; - - assert(mach.num < RubyConfig::numberOfMemories()); - assert(mach.num >= 0); - return mach; -} - -inline -NetDest getMultiStaticL2BankNetDest(const Address& addr, const Set& sharers) // set of L2RubyNodes +MachineID map_Address_to_DMA(const Address & addr) { - NetDest dest; - - for (int i = 0; i < sharers.getSize(); i++) { - if (sharers.isElement(i)) { - dest.add(map_L2ChipId_to_L2Cache(addr,i)); - } - } - return dest; + MachineID dma = {MachineType_DMA, 0}; + return dma; } +/* inline NetDest getOtherLocalL1IDs(MachineID L1) { @@ -244,119 +175,7 @@ NetDest getOtherLocalL1IDs(MachineID L1) return ret; } - -inline -NetDest getLocalL1IDs(MachineID mach) -{ - assert(MACHINETYPE_L1CACHE_ENUM != MachineType_NUM); - - NetDest ret; - - if (mach.type == MACHINETYPE_L1CACHE_ENUM) { - - int start = (mach.num / RubyConfig::numberOfL1CachePerChip()) * RubyConfig::numberOfProcsPerChip(); - - for (int i = start; i < (start + RubyConfig::numberOfProcsPerChip()); i++) { - MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i }; - ret.add( mach ); - } - } - else if (mach.type == MACHINETYPE_L2CACHE_ENUM) { - - int chip = mach.num/RubyConfig::numberOfL2CachePerChip(); - int start = ( chip*RubyConfig::numberOfL1CachePerChip()); - for (int i = start; i < (start + RubyConfig::numberOfL1CachePerChip()); i++) { - MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i }; - ret.add( mach ); - } - } - - return ret; -} - -inline -NetDest getExternalL1IDs(MachineID L1) -{ - NetDest ret; - - assert(MACHINETYPE_L1CACHE_ENUM != MachineType_NUM); - - for (int i = 0; i < RubyConfig::numberOfProcessors(); i++) { - // ret.add( (NodeID) i); - MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i }; - ret.add( mach ); - } - - ret.removeNetDest(getLocalL1IDs(L1)); - - return ret; -} - -inline -bool isLocalProcessor(MachineID thisId, MachineID tarID) -{ - int start = (thisId.num / RubyConfig::numberOfProcsPerChip()) * RubyConfig::numberOfProcsPerChip(); - - for (int i = start; i < (start + RubyConfig::numberOfProcsPerChip()); i++) { - if (i == tarID.num) { - return true; - } - } - return false; -} - - -inline -NetDest getAllPertinentL2Banks(const Address& addr) // set of L2RubyNodes -{ - NetDest dest; - - for (int i = 0; i < RubyConfig::numberOfChips(); i++) { - dest.add(map_L2ChipId_to_L2Cache(addr,i)); - } - return dest; -} - -inline -bool isL1OnChip(MachineID L1machID, NodeID L2NodeID) -{ - if (L1machID.type == MACHINETYPE_L1CACHE_ENUM) { - return (L1machID.num == L2NodeID); - } else { - return false; - } -} - -inline -bool isL2OnChip(MachineID L2machID, NodeID L2NodeID) -{ - if (L2machID.type == MACHINETYPE_L2CACHE_ENUM) { - return (L2machID.num == L2NodeID); - } else { - return false; - } -} - -inline -NodeID closest_clockwise_distance(NodeID this_node, NodeID next_node) -{ - if (this_node <= next_node) { - return (next_node - this_node); - } else { - return (next_node - this_node + RubyConfig::numberOfChips()); - } -} - -inline -bool closer_clockwise_processor(NodeID this_node, NodeID newer, NodeID older) -{ - return (closest_clockwise_distance(this_node, newer) < closest_clockwise_distance(this_node, older)); -} - -extern inline NodeID getChipID(MachineID L2machID) -{ - return (L2machID.num%RubyConfig::numberOfChips())/RubyConfig::numberOfProcsPerChip(); -} +*/ extern inline NodeID machineIDToNodeID(MachineID machID) { @@ -364,11 +183,6 @@ extern inline NodeID machineIDToNodeID(MachineID machID) return machID.num; } -extern inline NodeID machineIDToVersion(MachineID machID) -{ - return machID.num/RubyConfig::numberOfChips(); -} - extern inline MachineType machineIDToMachineType(MachineID machID) { return machID.type; @@ -379,25 +193,22 @@ extern inline NodeID L1CacheMachIDToProcessorNum(MachineID machID) assert(machID.type == MachineType_L1Cache); return machID.num; } - +/* extern inline NodeID L2CacheMachIDToChipID(MachineID machID) { assert(machID.type == MACHINETYPE_L2CACHE_ENUM); - return machID.num/RubyConfig::numberOfL2CachePerChip(); -} - -extern inline MachineID getCollectorDest(MachineID L1MachID) -{ - MachineID mach = {MACHINETYPE_COLLECTOR_ENUM, L1MachID.num}; - return mach; -} - -extern inline MachineID getCollectorL1Cache(MachineID colID) -{ - MachineID mach = {MACHINETYPE_L1CACHE_ENUM, colID.num}; - return mach; + int L2bank = machID.num; + int banks_seen = 0; + for (int i=0;i<RubyConfig::getNumberOfChips();i++) { + for (int j=0;j<RubyConfig::getNumberOfCachesPerLevelPerChip(2,i);j++) { + if (banks_seen == L2bank) + return i; + banks_seen++; + } + } + assert(0); } - +*/ extern inline MachineID getL1MachineID(NodeID L1RubyNode) { MachineID mach = {MACHINETYPE_L1CACHE_ENUM, L1RubyNode}; @@ -413,8 +224,6 @@ extern inline GenericMachineType ConvertMachToGenericMach(MachineType machType) return GenericMachineType_L3Cache; } else if (machType == MachineType_Directory) { return GenericMachineType_Directory; - } else if (machType == MACHINETYPE_COLLECTOR_ENUM) { - return GenericMachineType_Collector; } else { ERROR_MSG("cannot convert to a GenericMachineType"); return GenericMachineType_NULL; diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc b/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc index f16a02f26..6a12af385 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc +++ b/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc @@ -85,7 +85,7 @@ void profile_miss(const CacheMsg& msg, NodeID id) ASSERT (!Protocol::m_CMP); g_system_ptr->getProfiler()->addAddressTraceSample(msg, id); - g_system_ptr->getProfiler()->profileConflictingRequests(msg.getAddress()); + g_system_ptr->getProfiler()->profileConflictingRequests(msg.getLineAddress()); g_system_ptr->getProfiler()->addSecondaryStatSample(msg.getType(), msg.getAccessMode(), msg.getSize(), msg.getPrefetch(), id); @@ -93,9 +93,6 @@ void profile_miss(const CacheMsg& msg, NodeID id) void profile_L1Cache_miss(const CacheMsg& msg, NodeID id) { - // only called by protocols assuming non-zero cycle hits - ASSERT (REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH); - g_system_ptr->getProfiler()->addPrimaryStatSample(msg, id); } @@ -139,25 +136,5 @@ void profileGetS(const Address& datablock, const Address& PC, const Set& owner, g_system_ptr->getProfiler()->getAddressProfiler()->profileGetS(datablock, PC, owner, sharers, requestor); } -void profileOverflow(const Address & addr, MachineID mach) -{ -#if 0 - if(mach.type == MACHINETYPE_L1CACHE_ENUM){ - // for L1 overflows - int proc_num = L1CacheMachIDToProcessorNum(mach); - int chip_num = proc_num/RubyConfig::numberOfProcsPerChip(); - assert(0); - // g_system_ptr->getChip(chip_num)->m_L1Cache_xact_mgr_vec[proc_num]->profileOverflow(addr, true); - } - else if(mach.type == MACHINETYPE_L2CACHE_ENUM){ - // for L2 overflows - int chip_num = L2CacheMachIDToChipID(mach); - for(int p=0; p < RubyConfig::numberOfProcessors(); ++p){ - assert(0); - // g_system_ptr->getChip(chip_num)->m_L1Cache_xact_mgr_vec[p]->profileOverflow(addr, false); - } - } -#endif -} diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh index d0fc0c4a5..d8692951e 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh @@ -54,6 +54,7 @@ #include "mem/protocol/MessageSizeType.hh" #include "mem/ruby/network/Network.hh" #include "mem/protocol/PrefetchBit.hh" +#include "mem/ruby/system/System.hh" #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" @@ -67,7 +68,7 @@ extern inline int random(int n) extern inline bool multicast_retry() { - if (RANDOMIZATION) { + if (RubySystem::getRandomization()) { return (random() & 0x1); } else { return true; @@ -111,15 +112,18 @@ extern inline int MessageSizeTypeToInt(MessageSizeType size_type) return MessageSizeType_to_int(size_type); } +/* extern inline int numberOfNodes() { return RubyConfig::numberOfChips(); } - +*/ +/* extern inline int numberOfL1CachePerChip() { - return RubyConfig::numberOfL1CachePerChip(); + return RubyConfig::getNumberOfCachesPerLevelPerChip(1,0); } +*/ extern inline bool long_enough_ago(Time event) { @@ -149,7 +153,7 @@ extern inline Time getTimeMinusTime(Time t1, Time t2) extern inline Time getPreviousDelayedCycles(Time t1, Time t2) { - if (RANDOMIZATION) { // when randomizing delayed + if (RubySystem::getRandomization()) { // when randomizing delayed return 0; } else { return getTimeMinusTime(t1, t2); @@ -167,39 +171,40 @@ extern inline Time time_to_int(Time time) return time; } - +/* extern inline bool getFilteringEnabled() { - return g_FILTERING_ENABLED; + return RubyConfig::getFilteringEnabled(); } + extern inline int getRetryThreshold() { - return g_RETRY_THRESHOLD; + return RubyConfig::getRetryThreshold(); } extern inline int getFixedTimeoutLatency() { - return g_FIXED_TIMEOUT_LATENCY; + return RubyConfig::getFixedTimeoutLatency(); } extern inline int N_tokens() { // return N+1 to handle clean writeback - return g_PROCS_PER_CHIP + 1; + return RubyConfig::getProcsPerChip() + 1; // return 1; } extern inline bool distributedPersistentEnabled() { - return g_DISTRIBUTED_PERSISTENT_ENABLED; + return RubyConfig::getDistributedPersistentEnabled(); } extern inline bool getDynamicTimeoutEnabled() { - return g_DYNAMIC_TIMEOUT_ENABLED; + return RubyConfig::getDynamicTimeoutEnabled(); } - +*/ // Appends an offset to an address extern inline Address setOffset(Address addr, int offset) { |