diff options
Diffstat (limited to 'src/mem/ruby/slicc_interface')
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractCacheEntry.cc | 45 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractCacheEntry.hh | 81 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractChip.cc | 47 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractChip.hh | 126 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractProtocol.hh | 60 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/Message.hh | 91 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/NetworkMessage.hh | 115 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh | 425 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc | 163 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh | 73 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/RubySlicc_Util.hh | 219 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/RubySlicc_includes.hh | 9 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/SConscript | 38 |
13 files changed, 1492 insertions, 0 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc new file mode 100644 index 000000000..6bb936248 --- /dev/null +++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc @@ -0,0 +1,45 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $Id$ + * + * Description: See AbstractCacheEntry.h + * + */ + +#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" + +AbstractCacheEntry::AbstractCacheEntry() { +} + +// still need to define destructor for subclasses +AbstractCacheEntry::~AbstractCacheEntry() { +} + diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh new file mode 100644 index 000000000..18dc16ca8 --- /dev/null +++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh @@ -0,0 +1,81 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $Id$ + * + * Description: Common base class for a machine node. + * + */ + +#ifndef AbstractCacheEntry_H +#define AbstractCacheEntry_H + +#include "mem/ruby/common/Global.hh" +#include "mem/ruby/common/Address.hh" +#include "mem/protocol/AccessPermission.hh" + +class AbstractCacheEntry { +public: + // Constructors + AbstractCacheEntry(); + + // Destructor, prevent it from instantiation + virtual ~AbstractCacheEntry() = 0; + + // Public Methods + + // The methods below are those called by ruby runtime, add when it is + // absolutely necessary and should all be virtual function. + + + virtual void print(ostream& out) const = 0; + + // Data Members (m_ prefix) + Address m_Address; // Address of this block, required by CacheMemory + Time m_LastRef; // Last time this block was referenced, required by CacheMemory + AccessPermission m_Permission; // Access permission for this block, required by CacheMemory +}; + +// Output operator declaration +ostream& operator<<(ostream& out, const AbstractCacheEntry& obj); + +// ******************* Definitions ******************* + +// Output operator definition +extern inline +ostream& operator<<(ostream& out, const AbstractCacheEntry& obj) +{ + obj.print(out); + out << flush; + return out; +} + +#endif //AbstractCacheEntry_H + diff --git a/src/mem/ruby/slicc_interface/AbstractChip.cc b/src/mem/ruby/slicc_interface/AbstractChip.cc new file mode 100644 index 000000000..5ef39b238 --- /dev/null +++ b/src/mem/ruby/slicc_interface/AbstractChip.cc @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $Id$ + * + * Description: See AbstractChip.h + * + */ + +#include "mem/ruby/slicc_interface/AbstractChip.hh" + +AbstractChip::AbstractChip(NodeID id, Network* net_ptr) { + m_id = id; + m_net_ptr = net_ptr; + m_L1Cache_sequencer_vec.setSize(0); +} + +// still need to be defined for subclasses +AbstractChip::~AbstractChip() { +} diff --git a/src/mem/ruby/slicc_interface/AbstractChip.hh b/src/mem/ruby/slicc_interface/AbstractChip.hh new file mode 100644 index 000000000..d47dd6306 --- /dev/null +++ b/src/mem/ruby/slicc_interface/AbstractChip.hh @@ -0,0 +1,126 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $Id$ + * + * Description: Common base class for a machine chip. + * + */ + +#ifndef ABSTRACT_CHIP_H +#define ABSTRACT_CHIP_H + +#include "mem/ruby/common/Global.hh" +#include "mem/ruby/system/NodeID.hh" +#include "mem/ruby/config/RubyConfig.hh" +#include "mem/protocol/L1Cache_Entry.hh" +#include "mem/ruby/common/Address.hh" +#include "mem/gems_common/Vector.hh" + +class Network; +class Sequencer; +class StoreBuffer; +class ENTRY; +class MessageBuffer; +class CacheRecorder; +class TransactionInterfaceManager; + +template<class ENTRY> class CacheMemory; + +class AbstractChip { +public: + // Constructors + AbstractChip(NodeID chip_number, Network* net_ptr); + + // Destructor, prevent from being instantiated + virtual ~AbstractChip() = 0; + + // Public Methods + NodeID getID() const { return m_id; }; + Network* getNetwork() const { return m_net_ptr; }; + Sequencer* getSequencer(int index) const { return m_L1Cache_sequencer_vec[index]; }; + TransactionInterfaceManager* getTransactionInterfaceManager(int index) const { return m_L1Cache_xact_mgr_vec[index]; }; + void setTransactionInterfaceManager(TransactionInterfaceManager* manager, int index) { m_L1Cache_xact_mgr_vec[index] = manager; } + + // used when CHECK_COHERENCE is enabled. See RubySystem::checkGlobalCoherence() + virtual bool isBlockExclusive(const Address& addr) const { return false; } + virtual bool isBlockShared(const Address& addr) const { return false; } + + // cache dump functions + virtual void recordCacheContents(CacheRecorder& tr) const = 0; + virtual void dumpCaches(ostream& out) const = 0; + virtual void dumpCacheData(ostream& out) const = 0; + + virtual void printConfig(ostream& out) = 0; + virtual void print(ostream& out) const = 0; + + // pulic data structures + Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_L1DcacheMemory_vec; + Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_L1IcacheMemory_vec; + Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_cacheMemory_vec; + Vector < CacheMemory<L1Cache_Entry>* > m_L1Cache_L2cacheMemory_vec; + Vector < CacheMemory<L1Cache_Entry>* > m_L2Cache_L2cacheMemory_vec; + + // added so that the prefetcher and sequencer can access the L1 and L2 request queues + Vector < MessageBuffer* > m_L1Cache_optionalQueue_vec; + Vector < MessageBuffer* >m_L1Cache_mandatoryQueue_vec; + + // TSO storebuffer + Vector < StoreBuffer* > m_L1Cache_storeBuffer_vec; + + // TM transaction manager + Vector < TransactionInterfaceManager* > m_L1Cache_xact_mgr_vec; + +protected: + + // Data Members (m_ prefix) + NodeID m_id; // Chip id + Network* m_net_ptr; // Points to the Network simulator + Vector < Sequencer* > m_L1Cache_sequencer_vec; // All chip should have a sequencer + + +}; + +// Output operator declaration +ostream& operator<<(ostream& out, const AbstractChip& obj); + +// ******************* Definitions ******************* + +// Output operator definition +extern inline +ostream& operator<<(ostream& out, const AbstractChip& obj) +{ + obj.print(out); + out << flush; + return out; +} + +#endif //ABSTRACT_CHIP_H + diff --git a/src/mem/ruby/slicc_interface/AbstractProtocol.hh b/src/mem/ruby/slicc_interface/AbstractProtocol.hh new file mode 100644 index 000000000..d602f5e54 --- /dev/null +++ b/src/mem/ruby/slicc_interface/AbstractProtocol.hh @@ -0,0 +1,60 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $Id$ + * + * Description: Define all possible protocol parameters and their + * default value here. Normally, all parameters should + * have default value "false" means the feature of the + * protocol is turned off. + * + */ + +#ifndef AbstractProtocol_H +#define AbstractProtocol_H + +class AbstractProtocol { +public: + // Constructors + AbstractProtocol() {}; + + // Destructor, no instantiation + // No definition also, so no subclass can be instantiated also + virtual ~AbstractProtocol() = 0; + + // Public Methods + + // Data Members (m_ prefix) + static const bool m_CMP = false ; + static const bool m_TwoLevelCache = false ; +}; + +#endif //AbstractProtocol_H + diff --git a/src/mem/ruby/slicc_interface/Message.hh b/src/mem/ruby/slicc_interface/Message.hh new file mode 100644 index 000000000..c8917795b --- /dev/null +++ b/src/mem/ruby/slicc_interface/Message.hh @@ -0,0 +1,91 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $Id$ + */ + +#ifndef MESSAGE_H +#define MESSAGE_H + +#include "mem/ruby/common/Global.hh" +#include "mem/gems_common/RefCnt.hh" +#include "mem/gems_common/RefCountable.hh" +#include "mem/ruby/eventqueue/RubyEventQueue.hh" + +class Message; +typedef RefCnt<Message> MsgPtr; + +class Message : public RefCountable { +public: + // Constructors + Message() : RefCountable() { m_time = g_eventQueue_ptr->getTime(); m_LastEnqueueTime = g_eventQueue_ptr->getTime(); m_DelayedCycles = 0;} + + // Destructor + virtual ~Message() { } + + // Public Methods + virtual Message* clone() const = 0; + virtual void destroy() = 0; + virtual void print(ostream& out) const = 0; + + void setDelayedCycles(const int& cycles) { m_DelayedCycles = cycles; } + const int& getDelayedCycles() const {return m_DelayedCycles;} + int& getDelayedCycles() {return m_DelayedCycles;} + void setLastEnqueueTime(const Time& time) { m_LastEnqueueTime = time; } + const Time& getLastEnqueueTime() const {return m_LastEnqueueTime;} + Time& getLastEnqueueTime() {return m_LastEnqueueTime;} + + const Time& getTime() const { return m_time; } + void setTime(const Time& new_time) { m_time = new_time; } +private: + // Private Methods + + // Data Members (m_ prefix) + Time m_time; + Time m_LastEnqueueTime; // my last enqueue time + int m_DelayedCycles; // my delayed cycles + +}; + +// Output operator declaration +ostream& operator<<(ostream& out, const Message& obj); + +// ******************* Definitions ******************* + +// Output operator definition +extern inline +ostream& operator<<(ostream& out, const Message& obj) +{ + obj.print(out); + out << flush; + return out; +} + +#endif //MESSAGE_H diff --git a/src/mem/ruby/slicc_interface/NetworkMessage.hh b/src/mem/ruby/slicc_interface/NetworkMessage.hh new file mode 100644 index 000000000..81c7dc2b0 --- /dev/null +++ b/src/mem/ruby/slicc_interface/NetworkMessage.hh @@ -0,0 +1,115 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * NetworkMessage.h + * + * Description: + * + * $Id$ + * + */ + +#ifndef NetworkMessage_H +#define NetworkMessage_H + +#include "mem/ruby/common/Global.hh" +#include "mem/gems_common/RefCnt.hh" +#include "mem/gems_common/RefCountable.hh" +#include "mem/ruby/slicc_interface/Message.hh" +#include "mem/protocol/MessageSizeType.hh" +#include "mem/ruby/common/NetDest.hh" + +class Address; + +class NetworkMessage; +typedef RefCnt<NetworkMessage> NetMsgPtr; + +class NetworkMessage : public Message { +public: + // Constructors + NetworkMessage() + :Message() + { + m_internal_dest_valid = false; + } + + // Destructor + virtual ~NetworkMessage() { } + + // Public Methods + + virtual const NetDest& getDestination() const = 0; + virtual NetDest& getDestination() = 0; + virtual const MessageSizeType& getMessageSize() const = 0; + virtual MessageSizeType& getMessageSize() = 0; + // virtual const Address& getAddress() const = 0; + // virtual Address& getAddress() = 0; + + const NetDest& getInternalDestination() const { + if (m_internal_dest_valid == false) { + return getDestination(); + } else { + return m_internal_dest; + } + } + + NetDest& getInternalDestination() { + if (m_internal_dest_valid == false) { + m_internal_dest = getDestination(); + m_internal_dest_valid = true; + } + return m_internal_dest; + } + + virtual void print(ostream& out) const = 0; + +private: + // Private Methods + + // Data Members (m_ prefix) + NetDest m_internal_dest; + bool m_internal_dest_valid; +}; + +// Output operator declaration +ostream& operator<<(ostream& out, const NetworkMessage& obj); + +// ******************* Definitions ******************* + +// Output operator definition +extern inline +ostream& operator<<(ostream& out, const NetworkMessage& obj) +{ + obj.print(out); + out << flush; + return out; +} + +#endif //NetworkMessage_H diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh new file mode 100644 index 000000000..bf5778479 --- /dev/null +++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh @@ -0,0 +1,425 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * $Id$ + */ + +#ifndef COMPONENTMAPPINGFNS_H +#define COMPONENTMAPPINGFNS_H + +#include "mem/ruby/common/Global.hh" +#include "mem/ruby/config/RubyConfig.hh" +#include "mem/ruby/system/NodeID.hh" +#include "mem/ruby/system/MachineID.hh" +#include "mem/ruby/common/Address.hh" +#include "mem/ruby/common/Set.hh" +#include "mem/ruby/common/NetDest.hh" +#include "mem/protocol/GenericMachineType.hh" + +#ifdef MACHINETYPE_L1Cache +#define MACHINETYPE_L1CACHE_ENUM MachineType_L1Cache +#else +#define MACHINETYPE_L1CACHE_ENUM MachineType_NUM +#endif + +#ifdef MACHINETYPE_L2Cache +#define MACHINETYPE_L2CACHE_ENUM MachineType_L2Cache +#else +#define MACHINETYPE_L2CACHE_ENUM MachineType_NUM +#endif + +#ifdef MACHINETYPE_L3Cache +#define MACHINETYPE_L3CACHE_ENUM MachineType_L3Cache +#else +#define MACHINETYPE_L3CACHE_ENUM MachineType_NUM +#endif + +#ifdef MACHINETYPE_PersistentArbiter +#define MACHINETYPE_PERSISTENTARBITER_ENUM MachineType_PersistentArbiter +#else +#define MACHINETYPE_PERSISTENTARBITER_ENUM MachineType_NUM +#endif + +#ifdef MACHINETYPE_Collector +#define MACHINETYPE_COLLECTOR_ENUM MachineType_Collector +#else +#define MACHINETYPE_COLLECTOR_ENUM MachineType_NUM +#endif + + +// used to determine the correct L1 set +// input parameters are the address and number of set bits for the L1 cache +// returns a value between 0 and the total number of L1 cache sets +inline +int map_address_to_L1CacheSet(const Address& addr, int cache_num_set_bits) +{ + return addr.bitSelect(RubyConfig::dataBlockBits(), + RubyConfig::dataBlockBits()+cache_num_set_bits-1); +} + +// used to determine the correct L2 set +// input parameters are the address and number of set bits for the L2 cache +// returns a value between 0 and the total number of L2 cache sets +inline +int map_address_to_L2CacheSet(const Address& addr, int cache_num_set_bits) +{ + assert(cache_num_set_bits == L2_CACHE_NUM_SETS_BITS); // ensure the l2 bank mapping functions agree with l2 set bits + + if (MAP_L2BANKS_TO_LOWEST_BITS) { + return addr.bitSelect(RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits(), + RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits()+cache_num_set_bits-1); + } else { + return addr.bitSelect(RubyConfig::dataBlockBits(), + RubyConfig::dataBlockBits()+cache_num_set_bits-1); + } +} + +// input parameter is the base ruby node of the L1 cache +// returns a value between 0 and total_L2_Caches_within_the_system +inline +MachineID map_L1CacheMachId_to_L2Cache(const Address& addr, MachineID L1CacheMachId) +{ + int L2bank = 0; + MachineID mach = {MACHINETYPE_L2CACHE_ENUM, 0}; + + if (RubyConfig::L2CachePerChipBits() > 0) { + if (MAP_L2BANKS_TO_LOWEST_BITS) { + L2bank = addr.bitSelect(RubyConfig::dataBlockBits(), + RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits()-1); + } else { + L2bank = addr.bitSelect(RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS, + RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS+RubyConfig::L2CachePerChipBits()-1); + } + } + + assert(L2bank < RubyConfig::numberOfL2CachePerChip()); + assert(L2bank >= 0); + + mach.num = RubyConfig::L1CacheNumToL2Base(L1CacheMachId.num)*RubyConfig::numberOfL2CachePerChip() // base # + + L2bank; // bank # + assert(mach.num < RubyConfig::numberOfL2Cache()); + return mach; +} + +// used to determine the correct L2 bank +// input parameter is the base ruby node of the L2 cache +// returns a value between 0 and total_L2_Caches_within_the_system +inline +MachineID map_L2ChipId_to_L2Cache(const Address& addr, NodeID L2ChipId) +{ + assert(L2ChipId < RubyConfig::numberOfChips()); + + int L2bank = 0; + MachineID mach = {MACHINETYPE_L2CACHE_ENUM, 0}; + + if (RubyConfig::L2CachePerChipBits() > 0) { + if (MAP_L2BANKS_TO_LOWEST_BITS) { + L2bank = addr.bitSelect(RubyConfig::dataBlockBits(), + RubyConfig::dataBlockBits()+RubyConfig::L2CachePerChipBits()-1); + } else { + L2bank = addr.bitSelect(RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS, + RubyConfig::dataBlockBits()+L2_CACHE_NUM_SETS_BITS+RubyConfig::L2CachePerChipBits()-1); + } + } + + assert(L2bank < RubyConfig::numberOfL2CachePerChip()); + assert(L2bank >= 0); + + mach.num = L2ChipId*RubyConfig::numberOfL2CachePerChip() // base # + + L2bank; // bank # + assert(mach.num < RubyConfig::numberOfL2Cache()); + return mach; +} + +// used to determine the home directory +// returns a value between 0 and total_directories_within_the_system +inline +NodeID map_Address_to_DirectoryNode(const Address& addr) +{ + NodeID dirNode = 0; + + if (RubyConfig::memoryBits() > 0) { + dirNode = addr.bitSelect(RubyConfig::dataBlockBits(), + RubyConfig::dataBlockBits()+RubyConfig::memoryBits()-1); + } + + // Index indexHighPortion = address.bitSelect(MEMORY_SIZE_BITS-1, PAGE_SIZE_BITS+NUMBER_OF_MEMORY_MODULE_BITS); + // Index indexLowPortion = address.bitSelect(DATA_BLOCK_BITS, PAGE_SIZE_BITS-1); + + //Index index = indexLowPortion | (indexHighPortion << (PAGE_SIZE_BITS - DATA_BLOCK_BITS)); + +/* + +ADDRESS_WIDTH MEMORY_SIZE_BITS PAGE_SIZE_BITS DATA_BLOCK_BITS + | | | | + \ / \ / \ / \ / 0 + ----------------------------------------------------------------------- + | unused |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| | + | |xxxxxxxxxxxxxxx| |xxxxxxxxxxxxxxx| | + ----------------------------------------------------------------------- + indexHighPortion indexLowPortion + <-------> + NUMBER_OF_MEMORY_MODULE_BITS + */ + + assert(dirNode < RubyConfig::numberOfMemories()); + assert(dirNode >= 0); + return dirNode; +} + +// used to determine the home directory +// returns a value between 0 and total_directories_within_the_system +inline +MachineID map_Address_to_Directory(const Address &addr) +{ + MachineID mach = {MachineType_Directory, map_Address_to_DirectoryNode(addr)}; + return mach; +} + +inline +MachineID map_Address_to_CentralArbiterNode(const Address& addr) +{ + MachineType t = MACHINETYPE_PERSISTENTARBITER_ENUM; + MachineID mach = {t, map_Address_to_DirectoryNode(addr)}; + + assert(mach.num < RubyConfig::numberOfMemories()); + assert(mach.num >= 0); + return mach; +} + +inline +NetDest getMultiStaticL2BankNetDest(const Address& addr, const Set& sharers) // set of L2RubyNodes +{ + NetDest dest; + + for (int i = 0; i < sharers.getSize(); i++) { + if (sharers.isElement(i)) { + dest.add(map_L2ChipId_to_L2Cache(addr,i)); + } + } + return dest; +} + +inline +NetDest getOtherLocalL1IDs(MachineID L1) +{ + int start = (L1.num / RubyConfig::numberOfProcsPerChip()) * RubyConfig::numberOfProcsPerChip(); + NetDest ret; + + assert(MACHINETYPE_L1CACHE_ENUM != MachineType_NUM); + + for (int i = start; i < (start + RubyConfig::numberOfProcsPerChip()); i++) { + if (i != L1.num) { + MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i }; + ret.add( mach ); + } + } + + return ret; +} + +inline +NetDest getLocalL1IDs(MachineID mach) +{ + assert(MACHINETYPE_L1CACHE_ENUM != MachineType_NUM); + + NetDest ret; + + if (mach.type == MACHINETYPE_L1CACHE_ENUM) { + + int start = (mach.num / RubyConfig::numberOfL1CachePerChip()) * RubyConfig::numberOfProcsPerChip(); + + for (int i = start; i < (start + RubyConfig::numberOfProcsPerChip()); i++) { + MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i }; + ret.add( mach ); + } + } + else if (mach.type == MACHINETYPE_L2CACHE_ENUM) { + + int chip = mach.num/RubyConfig::numberOfL2CachePerChip(); + int start = ( chip*RubyConfig::numberOfL1CachePerChip()); + for (int i = start; i < (start + RubyConfig::numberOfL1CachePerChip()); i++) { + MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i }; + ret.add( mach ); + } + } + + return ret; +} + +inline +NetDest getExternalL1IDs(MachineID L1) +{ + NetDest ret; + + assert(MACHINETYPE_L1CACHE_ENUM != MachineType_NUM); + + for (int i = 0; i < RubyConfig::numberOfProcessors(); i++) { + // ret.add( (NodeID) i); + MachineID mach = { MACHINETYPE_L1CACHE_ENUM, i }; + ret.add( mach ); + } + + ret.removeNetDest(getLocalL1IDs(L1)); + + return ret; +} + +inline +bool isLocalProcessor(MachineID thisId, MachineID tarID) +{ + int start = (thisId.num / RubyConfig::numberOfProcsPerChip()) * RubyConfig::numberOfProcsPerChip(); + + for (int i = start; i < (start + RubyConfig::numberOfProcsPerChip()); i++) { + if (i == tarID.num) { + return true; + } + } + return false; +} + + +inline +NetDest getAllPertinentL2Banks(const Address& addr) // set of L2RubyNodes +{ + NetDest dest; + + for (int i = 0; i < RubyConfig::numberOfChips(); i++) { + dest.add(map_L2ChipId_to_L2Cache(addr,i)); + } + return dest; +} + +inline +bool isL1OnChip(MachineID L1machID, NodeID L2NodeID) +{ + if (L1machID.type == MACHINETYPE_L1CACHE_ENUM) { + return (L1machID.num == L2NodeID); + } else { + return false; + } +} + +inline +bool isL2OnChip(MachineID L2machID, NodeID L2NodeID) +{ + if (L2machID.type == MACHINETYPE_L2CACHE_ENUM) { + return (L2machID.num == L2NodeID); + } else { + return false; + } +} + +inline +NodeID closest_clockwise_distance(NodeID this_node, NodeID next_node) +{ + if (this_node <= next_node) { + return (next_node - this_node); + } else { + return (next_node - this_node + RubyConfig::numberOfChips()); + } +} + +inline +bool closer_clockwise_processor(NodeID this_node, NodeID newer, NodeID older) +{ + return (closest_clockwise_distance(this_node, newer) < closest_clockwise_distance(this_node, older)); +} + +extern inline NodeID getChipID(MachineID L2machID) +{ + return (L2machID.num%RubyConfig::numberOfChips())/RubyConfig::numberOfProcsPerChip(); +} + +extern inline NodeID machineIDToNodeID(MachineID machID) +{ + // return machID.num%RubyConfig::numberOfChips(); + return machID.num; +} + +extern inline NodeID machineIDToVersion(MachineID machID) +{ + return machID.num/RubyConfig::numberOfChips(); +} + +extern inline MachineType machineIDToMachineType(MachineID machID) +{ + return machID.type; +} + +extern inline NodeID L1CacheMachIDToProcessorNum(MachineID machID) +{ + assert(machID.type == MachineType_L1Cache); + return machID.num; +} + +extern inline NodeID L2CacheMachIDToChipID(MachineID machID) +{ + assert(machID.type == MACHINETYPE_L2CACHE_ENUM); + return machID.num/RubyConfig::numberOfL2CachePerChip(); +} + +extern inline MachineID getCollectorDest(MachineID L1MachID) +{ + MachineID mach = {MACHINETYPE_COLLECTOR_ENUM, L1MachID.num}; + return mach; +} + +extern inline MachineID getCollectorL1Cache(MachineID colID) +{ + MachineID mach = {MACHINETYPE_L1CACHE_ENUM, colID.num}; + return mach; +} + +extern inline MachineID getL1MachineID(NodeID L1RubyNode) +{ + MachineID mach = {MACHINETYPE_L1CACHE_ENUM, L1RubyNode}; + return mach; +} + +extern inline GenericMachineType ConvertMachToGenericMach(MachineType machType) { + if (machType == MACHINETYPE_L1CACHE_ENUM) { + return GenericMachineType_L1Cache; + } else if (machType == MACHINETYPE_L2CACHE_ENUM) { + return GenericMachineType_L2Cache; + } else if (machType == MACHINETYPE_L3CACHE_ENUM) { + return GenericMachineType_L3Cache; + } else if (machType == MachineType_Directory) { + return GenericMachineType_Directory; + } else if (machType == MACHINETYPE_COLLECTOR_ENUM) { + return GenericMachineType_Collector; + } else { + ERROR_MSG("cannot convert to a GenericMachineType"); + return GenericMachineType_NULL; + } +} + + +#endif // COMPONENTMAPPINGFNS_H diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc b/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc new file mode 100644 index 000000000..1c0435aca --- /dev/null +++ b/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.cc @@ -0,0 +1,163 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * slicc_util.C + * + * Description: See slicc_util.h + * + * $Id$ + * + */ + +#include "mem/ruby/common/Global.hh" +#include "mem/ruby/system/System.hh" +#include "mem/ruby/profiler/Profiler.hh" +#include "mem/ruby/profiler/AddressProfiler.hh" +#include "mem/protocol/Protocol.hh" +#include "mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh" +#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" +// #include "TransactionInterfaceManager.hh" + +void profile_request(int cache_state, Directory_State directory_state, GenericRequestType request_type) +{ + string requestStr = L1Cache_State_to_string(L1Cache_State(cache_state))+":"+ + Directory_State_to_string(directory_state)+":"+ + GenericRequestType_to_string(request_type); + g_system_ptr->getProfiler()->profileRequest(requestStr); +} + +void profile_request(const string& L1CacheState, const string& L2CacheState, const string& directoryState, const string& requestType) +{ + string requestStr = L1CacheState+":"+L2CacheState+":"+directoryState+":"+requestType; + g_system_ptr->getProfiler()->profileRequest(requestStr); +} + +void profile_outstanding_request(int outstanding) +{ + g_system_ptr->getProfiler()->profileOutstandingRequest(outstanding); +} + +void profile_outstanding_persistent_request(int outstanding) +{ + g_system_ptr->getProfiler()->profileOutstandingPersistentRequest(outstanding); +} + +void profile_average_latency_estimate(int latency) +{ + g_system_ptr->getProfiler()->profileAverageLatencyEstimate(latency); +} + +void profile_sharing(const Address& addr, AccessType type, NodeID requestor, const Set& sharers, const Set& owner) +{ + g_system_ptr->getProfiler()->profileSharing(addr, type, requestor, sharers, owner); +} + +void profile_miss(const CacheMsg& msg, NodeID id) +{ + // CMP profile address after L1 misses, not L2 + ASSERT (!Protocol::m_CMP); + g_system_ptr->getProfiler()->addAddressTraceSample(msg, id); + + g_system_ptr->getProfiler()->profileConflictingRequests(msg.getAddress()); + + g_system_ptr->getProfiler()->addSecondaryStatSample(msg.getType(), + msg.getAccessMode(), msg.getSize(), msg.getPrefetch(), id); +} + +void profile_L1Cache_miss(const CacheMsg& msg, NodeID id) +{ + // only called by protocols assuming non-zero cycle hits + ASSERT (REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH); + + g_system_ptr->getProfiler()->addPrimaryStatSample(msg, id); +} + +void profileMsgDelay(int virtualNetwork, int delayCycles) +{ + g_system_ptr->getProfiler()->profileMsgDelay(virtualNetwork, delayCycles); +} + +void profile_L2Cache_miss(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID nodeID) +{ + g_system_ptr->getProfiler()->addSecondaryStatSample(requestType, type, msgSize, pfBit, nodeID); +} + +void profile_token_retry(const Address& addr, AccessType type, int count) +{ + g_system_ptr->getProfiler()->getAddressProfiler()->profileRetry(addr, type, count); +} + +void profile_filter_action(int action) +{ + g_system_ptr->getProfiler()->profileFilterAction(action); +} + +void profile_persistent_prediction(const Address& addr, AccessType type) +{ + g_system_ptr->getProfiler()->getAddressProfiler()->profilePersistentPrediction(addr, type); +} + +void profile_multicast_retry(const Address& addr, int count) +{ + g_system_ptr->getProfiler()->profileMulticastRetry(addr, count); +} + +void profileGetX(const Address& datablock, const Address& PC, const Set& owner, const Set& sharers, NodeID requestor) +{ + g_system_ptr->getProfiler()->getAddressProfiler()->profileGetX(datablock, PC, owner, sharers, requestor); +} + +void profileGetS(const Address& datablock, const Address& PC, const Set& owner, const Set& sharers, NodeID requestor) +{ + g_system_ptr->getProfiler()->getAddressProfiler()->profileGetS(datablock, PC, owner, sharers, requestor); +} + +void profileOverflow(const Address & addr, MachineID mach) +{ +#if 0 + if(mach.type == MACHINETYPE_L1CACHE_ENUM){ + // for L1 overflows + int proc_num = L1CacheMachIDToProcessorNum(mach); + int chip_num = proc_num/RubyConfig::numberOfProcsPerChip(); + assert(0); + // g_system_ptr->getChip(chip_num)->m_L1Cache_xact_mgr_vec[proc_num]->profileOverflow(addr, true); + } + else if(mach.type == MACHINETYPE_L2CACHE_ENUM){ + // for L2 overflows + int chip_num = L2CacheMachIDToChipID(mach); + for(int p=0; p < RubyConfig::numberOfProcessors(); ++p){ + assert(0); + // g_system_ptr->getChip(chip_num)->m_L1Cache_xact_mgr_vec[p]->profileOverflow(addr, false); + } + } +#endif +} + + diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh b/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh new file mode 100644 index 000000000..6cc3c6cd2 --- /dev/null +++ b/src/mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh @@ -0,0 +1,73 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * slicc_util.h + * + * Description: These are the functions that exported to slicc from ruby. + * + * $Id$ + * + */ + +#ifndef RUBYSLICC_PROFILER_INTERFACE_H +#define RUBYSLICC_PROFILER_INTERFACE_H + +#include "mem/ruby/common/Global.hh" +#include "mem/ruby/profiler/Profiler.hh" +#include "mem/ruby/common/Address.hh" +#include "mem/protocol/L1Cache_State.hh" +#include "mem/protocol/AccessType.hh" +#include "mem/protocol/GenericRequestType.hh" +#include "mem/protocol/Directory_State.hh" +#include "mem/ruby/system/NodeID.hh" + +class Set; + +void profile_request(int cache_state, Directory_State directory_state, GenericRequestType request_type); +void profile_outstanding_persistent_request(int outstanding); +void profile_outstanding_request(int outstanding); +void profile_sharing(const Address& addr, AccessType type, NodeID requestor, const Set& sharers, const Set& owner); +void profile_request(const string& L1CacheStateStr, const string& L2CacheStateStr, const string& directoryStateStr, const string& requestTypeStr); +void profile_miss(const CacheMsg& msg, NodeID id); +void profile_L1Cache_miss(const CacheMsg& msg, NodeID id); +void profile_L2Cache_miss(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID l2cacheID); +void profile_token_retry(const Address& addr, AccessType type, int count); +void profile_filter_action(int action); +void profile_persistent_prediction(const Address& addr, AccessType type); +void profile_average_latency_estimate(int latency); +void profileMsgDelay(int virtualNetwork, int delayCycles); + +void profile_multicast_retry(const Address& addr, int count); +void profileGetX(const Address& datablock, const Address& PC, const Set& owner, const Set& sharers, NodeID requestor); +void profileGetS(const Address& datablock, const Address& PC, const Set& owner, const Set& sharers, NodeID requestor); + +void profileOverflow(const Address & addr, MachineID mach); + +#endif // RUBYSLICC_PROFILER_INTERFACE_H diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh new file mode 100644 index 000000000..d4db1bb28 --- /dev/null +++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh @@ -0,0 +1,219 @@ + +/* + * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * slicc_util.h + * + * Description: These are the functions that exported to slicc from ruby. + * + * $Id$ + * + */ + +#ifndef SLICC_UTIL_H +#define SLICC_UTIL_H + +#include "mem/ruby/common/Global.hh" +#include "mem/ruby/common/Address.hh" +#include "mem/ruby/system/NodeID.hh" +#include "mem/ruby/system/MachineID.hh" +#include "mem/ruby/config/RubyConfig.hh" +#include "mem/protocol/CacheMsg.hh" +#include "mem/protocol/GenericRequestType.hh" +#include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/AccessType.hh" +#include "mem/protocol/MachineType.hh" +#include "mem/protocol/Directory_State.hh" +#include "mem/protocol/L1Cache_State.hh" +#include "mem/protocol/MessageSizeType.hh" +#include "mem/ruby/network/Network.hh" +#include "mem/protocol/PrefetchBit.hh" + +#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" + +class Set; +class NetDest; + +extern inline int random(int n) +{ + return random() % n; +} + +extern inline bool multicast_retry() +{ + if (RANDOMIZATION) { + return (random() & 0x1); + } else { + return true; + } +} + +extern inline int cache_state_to_int(L1Cache_State state) +{ + return state; +} + +extern inline Time get_time() +{ + return g_eventQueue_ptr->getTime(); +} + +extern inline Time zero_time() +{ + return 0; +} + +extern inline NodeID intToID(int nodenum) +{ + NodeID id = nodenum; + return id; +} + +extern inline int IDToInt(NodeID id) +{ + int nodenum = id; + return nodenum; +} + +extern inline int addressToInt(Address addr) +{ + return (int) addr.getLineAddress(); +} + +extern inline int MessageSizeTypeToInt(MessageSizeType size_type) +{ + return MessageSizeType_to_int(size_type); +} + +extern inline int numberOfNodes() +{ + return RubyConfig::numberOfChips(); +} + +extern inline int numberOfL1CachePerChip() +{ + return RubyConfig::numberOfL1CachePerChip(); +} + +extern inline bool long_enough_ago(Time event) +{ + return ((get_time() - event) > 200); +} + +extern inline int getAddThenMod(int addend1, int addend2, int modulus) +{ + return (addend1 + addend2) % modulus; +} + +extern inline Time getTimeModInt(Time time, int modulus) +{ + return time % modulus; +} + +extern inline Time getTimePlusInt(Time addend1, int addend2) +{ + return (Time) addend1 + addend2; +} + +extern inline Time getTimeMinusTime(Time t1, Time t2) +{ + ASSERT(t1 >= t2); + return t1 - t2; +} + +extern inline Time getPreviousDelayedCycles(Time t1, Time t2) +{ + if (RANDOMIZATION) { // when randomizing delayed + return 0; + } else { + return getTimeMinusTime(t1, t2); + } +} + +extern inline void WARN_ERROR_TIME(Time time) +{ + WARN_EXPR(time); +} + +// Return type for time_to_int is "Time" and not "int" so we get a 64-bit integer +extern inline Time time_to_int(Time time) +{ + return time; +} + + +extern inline bool getFilteringEnabled() +{ + return g_FILTERING_ENABLED; +} + +extern inline int getRetryThreshold() +{ + return g_RETRY_THRESHOLD; +} + +extern inline int getFixedTimeoutLatency() +{ + return g_FIXED_TIMEOUT_LATENCY; +} + +extern inline int N_tokens() +{ + // return N+1 to handle clean writeback + return g_PROCS_PER_CHIP + 1; + // return 1; +} + +extern inline bool distributedPersistentEnabled() +{ + return g_DISTRIBUTED_PERSISTENT_ENABLED; +} + +extern inline bool getDynamicTimeoutEnabled() +{ + return g_DYNAMIC_TIMEOUT_ENABLED; +} + +// Appends an offset to an address +extern inline Address setOffset(Address addr, int offset) +{ + Address result = addr; + result.setOffset(offset); + return result; +} + +// Makes an address into a line address +extern inline Address makeLineAddress(Address addr) +{ + Address result = addr; + result.makeLineAddress(); + return result; +} + +#endif //SLICC_UTIL_H diff --git a/src/mem/ruby/slicc_interface/RubySlicc_includes.hh b/src/mem/ruby/slicc_interface/RubySlicc_includes.hh new file mode 100644 index 000000000..0ac5496c4 --- /dev/null +++ b/src/mem/ruby/slicc_interface/RubySlicc_includes.hh @@ -0,0 +1,9 @@ +#ifndef RUBYSLICC_INCLUDES_H +#define RUBYSLICC_INCLUDES_H + +#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" +#include "mem/ruby/slicc_interface/RubySlicc_Util.hh" +#include "mem/ruby/slicc_interface/RubySlicc_Profiler_interface.hh" + +#endif + diff --git a/src/mem/ruby/slicc_interface/SConscript b/src/mem/ruby/slicc_interface/SConscript new file mode 100644 index 000000000..0cb453209 --- /dev/null +++ b/src/mem/ruby/slicc_interface/SConscript @@ -0,0 +1,38 @@ +# -*- mode:python -*- + +# Copyright (c) 2009 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +Import('*') + +if not env['RUBY']: + Return() + +Source('AbstractCacheEntry.cc') +Source('AbstractChip.cc') +Source('RubySlicc_Profiler_interface.cc') |