diff options
Diffstat (limited to 'src/mem/ruby/slicc_interface')
-rw-r--r-- | src/mem/ruby/slicc_interface/AbstractCacheEntry.hh | 2 | ||||
-rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.hh | 2 | ||||
-rw-r--r-- | src/mem/ruby/slicc_interface/Controller.py | 2 | ||||
-rw-r--r-- | src/mem/ruby/slicc_interface/RubySlicc_Util.hh | 5 |
4 files changed, 5 insertions, 6 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh index 69333f481..e92f96fd5 100644 --- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh +++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh @@ -52,8 +52,6 @@ class AbstractCacheEntry : public AbstractEntry void changePermission(AccessPermission new_perm); Address m_Address; // Address of this block, required by CacheMemory - Time m_LastRef; // Last time this block was referenced, required - // by CacheMemory int m_locked; // Holds info whether the address is locked, // required for implementing LL/SC }; diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index c452da723..44981a7e8 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -106,7 +106,7 @@ class AbstractController : public ClockedObject, public Consumer protected: int m_transitions_per_cycle; int m_buffer_size; - int m_recycle_latency; + Cycles m_recycle_latency; std::string m_name; NodeID m_version; Network* m_net_ptr; diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py index aa8f35145..5c2fd9b71 100644 --- a/src/mem/ruby/slicc_interface/Controller.py +++ b/src/mem/ruby/slicc_interface/Controller.py @@ -40,6 +40,6 @@ class RubyController(ClockedObject): transitions_per_cycle = \ Param.Int(32, "no. of SLICC state machine transitions per cycle") buffer_size = Param.Int(0, "max buffer size 0 means infinite") - recycle_latency = Param.Int(10, "") + recycle_latency = Param.Cycles(10, "") number_of_TBEs = Param.Int(256, "") ruby_system = Param.RubySystem(""); diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh index f55b6eae4..622efd04c 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh @@ -37,9 +37,8 @@ #include "debug/RubySlicc.hh" #include "mem/ruby/common/Address.hh" -#include "mem/ruby/common/Global.hh" #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" -#include "mem/ruby/system/System.hh" +#include "mem/packet.hh" inline int random(int n) @@ -53,6 +52,8 @@ zero_time() return 0; } +inline Cycles TimeToCycles(Time t) { return Cycles(t); } + inline NodeID intToID(int nodenum) { |