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-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.cc2
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.hh12
-rw-r--r--src/mem/ruby/slicc_interface/Controller.py3
-rw-r--r--src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh10
4 files changed, 17 insertions, 10 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 26cf91e9f..e46158ca0 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -35,6 +35,8 @@ AbstractController::AbstractController(const Params *p)
m_request_count(0)
{
m_version = p->version;
+ m_clusterID = p->cluster_id;
+
m_transitions_per_cycle = p->transitions_per_cycle;
m_buffer_size = p->buffer_size;
m_recycle_latency = p->recycle_latency;
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 3bf331c62..345eefa0a 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -56,7 +56,7 @@ class AbstractController : public ClockedObject, public Consumer
void init();
const Params *params() const { return (const Params *)_params; }
- const int & getVersion() const { return m_version; }
+ const NodeID getVersion() const { return m_version; }
void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
// return instance name
@@ -133,13 +133,12 @@ class AbstractController : public ClockedObject, public Consumer
void wakeUpAllBuffers();
protected:
- int m_transitions_per_cycle;
- int m_buffer_size;
- Cycles m_recycle_latency;
std::string m_name;
NodeID m_version;
- Network* m_net_ptr;
MachineID m_machineID;
+ NodeID m_clusterID;
+
+ Network* m_net_ptr;
bool m_is_blocking;
std::map<Address, MessageBuffer*> m_block_map;
typedef std::vector<MessageBuffer*> MsgVecType;
@@ -148,6 +147,9 @@ class AbstractController : public ClockedObject, public Consumer
unsigned int m_in_ports;
unsigned int m_cur_in_port;
int m_number_of_TBEs;
+ int m_transitions_per_cycle;
+ int m_buffer_size;
+ Cycles m_recycle_latency;
//! Map from physical network number to the Message Buffer.
std::map<uint32_t, MessageBuffer*> peerQueueMap;
diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py
index f8242322e..638d50b61 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -36,7 +36,8 @@ class RubyController(ClockedObject):
cxx_header = "mem/ruby/slicc_interface/AbstractController.hh"
abstract = True
version = Param.Int("")
- cntrl_id = Param.Int("")
+ cluster_id = Param.UInt32(0, "Id of this controller's cluster")
+
transitions_per_cycle = \
Param.Int(32, "no. of SLICC state machine transitions per cycle")
buffer_size = Param.Int(0, "max buffer size 0 means infinite")
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
index cb9830446..4df57c712 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
@@ -58,7 +58,7 @@ inline NetDest
broadcast(MachineType type)
{
NetDest dest;
- for (int i = 0; i < MachineType_base_count(type); i++) {
+ for (NodeID i = 0; i < MachineType_base_count(type); i++) {
MachineID mach = {type, i};
dest.add(mach);
}
@@ -67,12 +67,14 @@ broadcast(MachineType type)
inline MachineID
mapAddressToRange(const Address & addr, MachineType type, int low_bit,
- int num_bits)
+ int num_bits, int cluster_id = 0)
{
MachineID mach = {type, 0};
if (num_bits == 0)
- return mach;
- mach.num = addr.bitSelect(low_bit, low_bit + num_bits - 1);
+ mach.num = cluster_id;
+ else
+ mach.num = addr.bitSelect(low_bit, low_bit + num_bits - 1)
+ + (1 << num_bits) * cluster_id;
return mach;
}