2 files changed, 7 insertions, 0 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 0bc88eefa..b920ff7b0 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -360,6 +360,12 @@ AbstractController::recvTimingResp(PacketPtr pkt)
     delete pkt;
 }
 
+Tick
+AbstractController::recvAtomic(PacketPtr pkt)
+{
+   return ticksToCycles(memoryPort.sendAtomic(pkt));
+}
+
 MachineID
 AbstractController::mapAddressToMachine(Addr addr, MachineType mtype) const
 {
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 354dc80aa..35cd3d2a5 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -135,6 +135,7 @@ class AbstractController : public MemObject, public Consumer
     void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency,
                                  const DataBlock &block, int size);
     void recvTimingResp(PacketPtr pkt);
+    Tick recvAtomic(PacketPtr pkt);
 
     const AddrRangeList &getAddrRanges() const { return addrRanges; }