diff options
Diffstat (limited to 'src/mem/ruby/slicc_interface')
-rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.cc | 19 | ||||
-rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.hh | 9 |
2 files changed, 9 insertions, 19 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index dfcd61ab2..6bc5a9b96 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -41,16 +41,8 @@ AbstractController::AbstractController(const Params *p) m_number_of_TBEs(p->number_of_TBEs), m_transitions_per_cycle(p->transitions_per_cycle), m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency), - memoryPort(csprintf("%s.memory", name()), this, ""), - m_responseFromMemory_ptr(new MessageBuffer()) + memoryPort(csprintf("%s.memory", name()), this, "") { - // Set the sender pointer of the response message buffer from the - // memory controller. - // This pointer is used for querying for the current time. - m_responseFromMemory_ptr->setSender(this); - m_responseFromMemory_ptr->setReceiver(this); - m_responseFromMemory_ptr->setOrdering(false); - if (m_version == 0) { // Combine the statistics from all controllers // of this particular type. @@ -68,6 +60,9 @@ AbstractController::init() m_delayVCHistogram.push_back(new Stats::Histogram()); m_delayVCHistogram[i]->init(10); } + if (getMemoryQueue()) { + getMemoryQueue()->setSender(this); + } } void @@ -298,9 +293,6 @@ AbstractController::functionalMemoryWrite(PacketPtr pkt) { int num_functional_writes = 0; - // Check the message buffer that runs from the memory to the controller. - num_functional_writes += m_responseFromMemory_ptr->functionalWrite(pkt); - // Check the buffer from the controller to the memory. if (memoryPort.checkFunctional(pkt)) { num_functional_writes++; @@ -314,6 +306,7 @@ AbstractController::functionalMemoryWrite(PacketPtr pkt) void AbstractController::recvTimingResp(PacketPtr pkt) { + assert(getMemoryQueue()); assert(pkt->isResponse()); std::shared_ptr<MemoryMsg> msg = std::make_shared<MemoryMsg>(clockEdge()); @@ -338,7 +331,7 @@ AbstractController::recvTimingResp(PacketPtr pkt) panic("Incorrect packet type received from memory controller!"); } - m_responseFromMemory_ptr->enqueue(msg); + getMemoryQueue()->enqueue(msg); delete pkt; } diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index aadf03bd8..afde97b1f 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -75,6 +75,7 @@ class AbstractController : public MemObject, public Consumer void unblock(Address); virtual MessageBuffer* getMandatoryQueue() const = 0; + virtual MessageBuffer* getMemoryQueue() const = 0; virtual AccessPermission getAccessPermission(const Address& addr) = 0; virtual void print(std::ostream & out) const = 0; @@ -105,8 +106,8 @@ class AbstractController : public MemObject, public Consumer virtual void collateStats() {fatal("collateStats() should be overridden!");} - //! Set the message buffer with given name. - virtual void setNetQueue(const std::string& name, MessageBuffer *b) = 0; + //! Initialize the message buffers. + virtual void initNetQueues() = 0; /** A function used to return the port associated with this bus object. */ BaseMasterPort& getMasterPort(const std::string& if_name, @@ -210,10 +211,6 @@ class AbstractController : public MemObject, public Consumer /* Master port to the memory controller. */ MemoryPort memoryPort; - // Message Buffer for storing the response received from the - // memory controller. - MessageBuffer *m_responseFromMemory_ptr; - // State that is stored in packets sent to the memory controller. struct SenderState : public Packet::SenderState { |