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-rw-r--r--src/mem/ruby/slicc_interface/AbstractCacheEntry.cc2
-rw-r--r--src/mem/ruby/slicc_interface/AbstractCacheEntry.hh2
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.cc29
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.hh28
-rw-r--r--src/mem/ruby/slicc_interface/RubyRequest.cc2
-rw-r--r--src/mem/ruby/slicc_interface/RubyRequest.hh17
-rw-r--r--src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh8
-rw-r--r--src/mem/ruby/slicc_interface/RubySlicc_Util.hh56
8 files changed, 55 insertions, 89 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
index 137a6c950..01fd3f522 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
@@ -31,7 +31,7 @@
AbstractCacheEntry::AbstractCacheEntry()
{
m_Permission = AccessPermission_NotPresent;
- m_Address.setAddress(0);
+ m_Address = 0;
m_locked = -1;
}
diff --git a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
index 2ba128493..6c7a4a008 100644
--- a/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
+++ b/src/mem/ruby/slicc_interface/AbstractCacheEntry.hh
@@ -57,7 +57,7 @@ class AbstractCacheEntry : public AbstractEntry
{ panic("getDataBlk() not implemented!"); }
- Address m_Address; // Address of this block, required by CacheMemory
+ Addr m_Address; // Address of this block, required by CacheMemory
int m_locked; // Holds info whether the address is locked,
// required for implementing LL/SC
};
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 64d581359..9ed8b08d0 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -93,7 +93,7 @@ AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
}
void
-AbstractController::stallBuffer(MessageBuffer* buf, Address addr)
+AbstractController::stallBuffer(MessageBuffer* buf, Addr addr)
{
if (m_waiting_buffers.count(addr) == 0) {
MsgVecType* msgVec = new MsgVecType;
@@ -107,7 +107,7 @@ AbstractController::stallBuffer(MessageBuffer* buf, Address addr)
}
void
-AbstractController::wakeUpBuffers(Address addr)
+AbstractController::wakeUpBuffers(Addr addr)
{
if (m_waiting_buffers.count(addr) > 0) {
//
@@ -127,7 +127,7 @@ AbstractController::wakeUpBuffers(Address addr)
}
void
-AbstractController::wakeUpAllBuffers(Address addr)
+AbstractController::wakeUpAllBuffers(Addr addr)
{
if (m_waiting_buffers.count(addr) > 0) {
//
@@ -186,14 +186,14 @@ AbstractController::wakeUpAllBuffers()
}
void
-AbstractController::blockOnQueue(Address addr, MessageBuffer* port)
+AbstractController::blockOnQueue(Addr addr, MessageBuffer* port)
{
m_is_blocking = true;
m_block_map[addr] = port;
}
void
-AbstractController::unblock(Address addr)
+AbstractController::unblock(Addr addr)
{
m_block_map.erase(addr);
if (m_block_map.size() == 0) {
@@ -209,11 +209,10 @@ AbstractController::getMasterPort(const std::string &if_name,
}
void
-AbstractController::queueMemoryRead(const MachineID &id, Address addr,
+AbstractController::queueMemoryRead(const MachineID &id, Addr addr,
Cycles latency)
{
- RequestPtr req = new Request(addr.getAddress(),
- RubySystem::getBlockSizeBytes(), 0,
+ RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
m_masterId);
PacketPtr pkt = Packet::createRead(req);
@@ -234,11 +233,10 @@ AbstractController::queueMemoryRead(const MachineID &id, Address addr,
}
void
-AbstractController::queueMemoryWrite(const MachineID &id, Address addr,
+AbstractController::queueMemoryWrite(const MachineID &id, Addr addr,
Cycles latency, const DataBlock &block)
{
- RequestPtr req = new Request(addr.getAddress(),
- RubySystem::getBlockSizeBytes(), 0,
+ RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
m_masterId);
PacketPtr pkt = Packet::createWrite(req);
@@ -262,18 +260,17 @@ AbstractController::queueMemoryWrite(const MachineID &id, Address addr,
}
void
-AbstractController::queueMemoryWritePartial(const MachineID &id, Address addr,
+AbstractController::queueMemoryWritePartial(const MachineID &id, Addr addr,
Cycles latency,
const DataBlock &block, int size)
{
- RequestPtr req = new Request(addr.getAddress(),
- RubySystem::getBlockSizeBytes(), 0,
+ RequestPtr req = new Request(addr, RubySystem::getBlockSizeBytes(), 0,
m_masterId);
PacketPtr pkt = Packet::createWrite(req);
uint8_t *newData = new uint8_t[size];
pkt->dataDynamic(newData);
- memcpy(newData, block.getData(addr.getOffset(), size), size);
+ memcpy(newData, block.getData(getOffset(addr), size), size);
SenderState *s = new SenderState(id);
pkt->pushSenderState(s);
@@ -310,7 +307,7 @@ AbstractController::recvTimingResp(PacketPtr pkt)
assert(pkt->isResponse());
std::shared_ptr<MemoryMsg> msg = std::make_shared<MemoryMsg>(clockEdge());
- (*msg).m_addr.setAddress(pkt->getAddr());
+ (*msg).m_addr = pkt->getAddr();
(*msg).m_Sender = m_machineID;
SenderState *s = dynamic_cast<SenderState *>(pkt->senderState);
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index afde97b1f..94361034a 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -71,12 +71,12 @@ class AbstractController : public MemObject, public Consumer
void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
// return instance name
- void blockOnQueue(Address, MessageBuffer*);
- void unblock(Address);
+ void blockOnQueue(Addr, MessageBuffer*);
+ void unblock(Addr);
virtual MessageBuffer* getMandatoryQueue() const = 0;
virtual MessageBuffer* getMemoryQueue() const = 0;
- virtual AccessPermission getAccessPermission(const Address& addr) = 0;
+ virtual AccessPermission getAccessPermission(const Addr &addr) = 0;
virtual void print(std::ostream & out) const = 0;
virtual void wakeup() = 0;
@@ -88,16 +88,16 @@ class AbstractController : public MemObject, public Consumer
//! These functions are used by ruby system to read/write the data blocks
//! that exist with in the controller.
- virtual void functionalRead(const Address &addr, PacketPtr) = 0;
+ virtual void functionalRead(const Addr &addr, PacketPtr) = 0;
void functionalMemoryRead(PacketPtr);
//! The return value indicates the number of messages written with the
//! data from the packet.
virtual int functionalWriteBuffers(PacketPtr&) = 0;
- virtual int functionalWrite(const Address &addr, PacketPtr) = 0;
+ virtual int functionalWrite(const Addr &addr, PacketPtr) = 0;
int functionalMemoryWrite(PacketPtr);
//! Function for enqueuing a prefetch request
- virtual void enqueuePrefetch(const Address&, const RubyRequestType&)
+ virtual void enqueuePrefetch(const Addr &, const RubyRequestType&)
{ fatal("Prefetches not implemented!");}
//! Function for collating statistics from all the controllers of this
@@ -113,10 +113,10 @@ class AbstractController : public MemObject, public Consumer
BaseMasterPort& getMasterPort(const std::string& if_name,
PortID idx = InvalidPortID);
- void queueMemoryRead(const MachineID &id, Address addr, Cycles latency);
- void queueMemoryWrite(const MachineID &id, Address addr, Cycles latency,
+ void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency);
+ void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency,
const DataBlock &block);
- void queueMemoryWritePartial(const MachineID &id, Address addr, Cycles latency,
+ void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency,
const DataBlock &block, int size);
void recvTimingResp(PacketPtr pkt);
@@ -133,9 +133,9 @@ class AbstractController : public MemObject, public Consumer
//! Profiles the delay associated with messages.
void profileMsgDelay(uint32_t virtualNetwork, Cycles delay);
- void stallBuffer(MessageBuffer* buf, Address addr);
- void wakeUpBuffers(Address addr);
- void wakeUpAllBuffers(Address addr);
+ void stallBuffer(MessageBuffer* buf, Addr addr);
+ void wakeUpBuffers(Addr addr);
+ void wakeUpAllBuffers(Addr addr);
void wakeUpAllBuffers();
protected:
@@ -148,11 +148,11 @@ class AbstractController : public MemObject, public Consumer
Network* m_net_ptr;
bool m_is_blocking;
- std::map<Address, MessageBuffer*> m_block_map;
+ std::map<Addr, MessageBuffer*> m_block_map;
typedef std::vector<MessageBuffer*> MsgVecType;
typedef std::set<MessageBuffer*> MsgBufType;
- typedef std::map< Address, MsgVecType* > WaitingBufType;
+ typedef std::map<Addr, MsgVecType* > WaitingBufType;
WaitingBufType m_waiting_buffers;
unsigned int m_in_ports;
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.cc b/src/mem/ruby/slicc_interface/RubyRequest.cc
index e2f275006..350508671 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.cc
+++ b/src/mem/ruby/slicc_interface/RubyRequest.cc
@@ -69,7 +69,7 @@ RubyRequest::functionalWrite(Packet *pkt)
Addr wBase = pkt->getAddr();
Addr wTail = wBase + pkt->getSize();
- Addr mBase = m_PhysicalAddress.getAddress();
+ Addr mBase = m_PhysicalAddress;
Addr mTail = mBase + m_Size;
const uint8_t * pktData = pkt->getConstPtr<uint8_t>();
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh b/src/mem/ruby/slicc_interface/RubyRequest.hh
index cdb04bceb..b17269a78 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.hh
+++ b/src/mem/ruby/slicc_interface/RubyRequest.hh
@@ -40,10 +40,10 @@
class RubyRequest : public Message
{
public:
- Address m_PhysicalAddress;
- Address m_LineAddress;
+ Addr m_PhysicalAddress;
+ Addr m_LineAddress;
RubyRequestType m_Type;
- Address m_ProgramCounter;
+ Addr m_ProgramCounter;
RubyAccessMode m_AccessMode;
int m_Size;
PrefetchBit m_Prefetch;
@@ -66,18 +66,17 @@ class RubyRequest : public Message
pkt(_pkt),
m_contextId(_proc_id)
{
- m_LineAddress = m_PhysicalAddress;
- m_LineAddress.makeLineAddress();
+ m_LineAddress = makeLineAddress(m_PhysicalAddress);
}
RubyRequest(Tick curTime) : Message(curTime) {}
MsgPtr clone() const
{ return std::shared_ptr<Message>(new RubyRequest(*this)); }
- const Address& getLineAddress() const { return m_LineAddress; }
- const Address& getPhysicalAddress() const { return m_PhysicalAddress; }
+ Addr getLineAddress() const { return m_LineAddress; }
+ Addr getPhysicalAddress() const { return m_PhysicalAddress; }
const RubyRequestType& getType() const { return m_Type; }
- const Address& getProgramCounter() const { return m_ProgramCounter; }
+ Addr getProgramCounter() const { return m_ProgramCounter; }
const RubyAccessMode& getAccessMode() const { return m_AccessMode; }
const int& getSize() const { return m_Size; }
const PrefetchBit& getPrefetch() const { return m_Prefetch; }
@@ -95,4 +94,4 @@ operator<<(std::ostream& out, const RubyRequest& obj)
return out;
}
-#endif
+#endif // __MEM_RUBY_SLICC_INTERFACE_RUBY_REQUEST_HH__
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
index 14d24f028..46071335e 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
@@ -38,7 +38,7 @@
// used to determine the home directory
// returns a value between 0 and total_directories_within_the_system
inline NodeID
-map_Address_to_DirectoryNode(const Address& addr)
+map_Address_to_DirectoryNode(Addr addr)
{
return DirectoryMemory::mapAddressToDirectoryVersion(addr);
}
@@ -46,7 +46,7 @@ map_Address_to_DirectoryNode(const Address& addr)
// used to determine the home directory
// returns a value between 0 and total_directories_within_the_system
inline MachineID
-map_Address_to_Directory(const Address &addr)
+map_Address_to_Directory(Addr addr)
{
MachineID mach =
{MachineType_Directory, map_Address_to_DirectoryNode(addr)};
@@ -65,14 +65,14 @@ broadcast(MachineType type)
}
inline MachineID
-mapAddressToRange(const Address & addr, MachineType type, int low_bit,
+mapAddressToRange(Addr addr, MachineType type, int low_bit,
int num_bits, int cluster_id = 0)
{
MachineID mach = {type, 0};
if (num_bits == 0)
mach.num = cluster_id;
else
- mach.num = addr.bitSelect(low_bit, low_bit + num_bits - 1)
+ mach.num = bitSelect(addr, low_bit, low_bit + num_bits - 1)
+ (1 << num_bits) * cluster_id;
return mach;
}
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
index 6318d8e33..61813bb30 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh
@@ -36,9 +36,10 @@
#include <cassert>
#include "debug/RubySlicc.hh"
+#include "mem/packet.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/DataBlock.hh"
-#include "mem/packet.hh"
+#include "mem/ruby/common/TypeDefines.hh"
inline Cycles zero_time() { return Cycles(0); }
@@ -57,35 +58,10 @@ IDToInt(NodeID id)
}
inline int
-addressToInt(Address addr)
-{
- assert(!(addr.getAddress() & 0xffffffff00000000));
-
- return (int)addr.getAddress();
-}
-
-// Appends an offset to an address
-inline Address
-setOffset(Address addr, int offset)
+addressToInt(Addr addr)
{
- Address result = addr;
- result.setOffset(offset);
- return result;
-}
-
-// Makes an address into a line address
-inline Address
-makeLineAddress(Address addr)
-{
- Address result = addr;
- result.makeLineAddress();
- return result;
-}
-
-inline int
-addressOffset(Address addr)
-{
- return addr.getOffset();
+ assert(!(addr & 0xffffffff00000000));
+ return addr;
}
inline int
@@ -106,18 +82,15 @@ inline int max_tokens()
* returned if the data block was read, otherwise false is returned.
*/
inline bool
-testAndRead(Address addr, DataBlock& blk, Packet *pkt)
+testAndRead(Addr addr, DataBlock& blk, Packet *pkt)
{
- Address pktLineAddr(pkt->getAddr());
- pktLineAddr.makeLineAddress();
-
- Address lineAddr = addr;
- lineAddr.makeLineAddress();
+ Addr pktLineAddr = makeLineAddress(pkt->getAddr());
+ Addr lineAddr = makeLineAddress(addr);
if (pktLineAddr == lineAddr) {
uint8_t *data = pkt->getPtr<uint8_t>();
unsigned int size_in_bytes = pkt->getSize();
- unsigned startByte = pkt->getAddr() - lineAddr.getAddress();
+ unsigned startByte = pkt->getAddr() - lineAddr;
for (unsigned i = 0; i < size_in_bytes; ++i) {
data[i] = blk.getByte(i + startByte);
@@ -134,18 +107,15 @@ testAndRead(Address addr, DataBlock& blk, Packet *pkt)
* returned if the data block was written, otherwise false is returned.
*/
inline bool
-testAndWrite(Address addr, DataBlock& blk, Packet *pkt)
+testAndWrite(Addr addr, DataBlock& blk, Packet *pkt)
{
- Address pktLineAddr(pkt->getAddr());
- pktLineAddr.makeLineAddress();
-
- Address lineAddr = addr;
- lineAddr.makeLineAddress();
+ Addr pktLineAddr = makeLineAddress(pkt->getAddr());
+ Addr lineAddr = makeLineAddress(addr);
if (pktLineAddr == lineAddr) {
const uint8_t *data = pkt->getConstPtr<uint8_t>();
unsigned int size_in_bytes = pkt->getSize();
- unsigned startByte = pkt->getAddr() - lineAddr.getAddress();
+ unsigned startByte = pkt->getAddr() - lineAddr;
for (unsigned i = 0; i < size_in_bytes; ++i) {
blk.setByte(i + startByte, data[i]);
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-08 21:08:22 +0000