diff options
Diffstat (limited to 'src/mem/ruby/slicc_interface')
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.cc | 3 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/AbstractController.hh | 10 | ||||
| -rw-r--r-- | src/mem/ruby/slicc_interface/Controller.py | 10 |
3 files changed, 20 insertions, 3 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc index 68edcba59..c953e8257 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017,2019 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -55,6 +55,7 @@ AbstractController::AbstractController(const Params *p) m_number_of_TBEs(p->number_of_TBEs), m_transitions_per_cycle(p->transitions_per_cycle), m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency), + m_mandatory_queue_latency(p->mandatory_queue_latency), memoryPort(csprintf("%s.memory", name()), this, ""), addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()) { diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh index 4d0654698..8888bd0a7 100644 --- a/src/mem/ruby/slicc_interface/AbstractController.hh +++ b/src/mem/ruby/slicc_interface/AbstractController.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017,2019 ARM Limited * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -102,6 +102,13 @@ class AbstractController : public ClockedObject, public Consumer virtual Sequencer* getCPUSequencer() const = 0; virtual GPUCoalescer* getGPUCoalescer() const = 0; + // This latency is used by the sequencer when enqueueing requests. + // Different latencies may be used depending on the request type. + // This is the hit latency unless the top-level cache controller + // introduces additional cycles in the response path. + virtual Cycles mandatoryQueueLatency(const RubyRequestType& param_type) + { return m_mandatory_queue_latency; } + //! These functions are used by ruby system to read/write the data blocks //! that exist with in the controller. virtual void functionalRead(const Addr &addr, PacketPtr) = 0; @@ -195,6 +202,7 @@ class AbstractController : public ClockedObject, public Consumer const int m_transitions_per_cycle; const unsigned int m_buffer_size; Cycles m_recycle_latency; + const Cycles m_mandatory_queue_latency; //! Counter for the number of cycles when the transitions carried out //! were equal to the maximum allowed diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py index 4d3c1900e..de48929b6 100644 --- a/src/mem/ruby/slicc_interface/Controller.py +++ b/src/mem/ruby/slicc_interface/Controller.py @@ -1,4 +1,4 @@ -# Copyright (c) 2017 ARM Limited +# Copyright (c) 2017,2019 ARM Limited # All rights reserved. # # The license below extends only to copyright in the software and shall @@ -61,5 +61,13 @@ class RubyController(ClockedObject): number_of_TBEs = Param.Int(256, "") ruby_system = Param.RubySystem("") + # This is typically a proxy to the icache/dcache hit latency. + # If the latency depends on the request type or protocol-specific states, + # the protocol may ignore this parameter by overriding the + # mandatoryQueueLatency function + mandatory_queue_latency = \ + Param.Cycles(1, "Default latency for requests added to the " \ + "mandatory queue on top-level controllers") + memory = MasterPort("Port for attaching a memory controller") system = Param.System(Parent.any, "system object parameter") |