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-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.cc5
-rw-r--r--src/mem/ruby/slicc_interface/AbstractController.hh4
2 files changed, 4 insertions, 5 deletions
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index 1327eccfb..fa1c936b7 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -229,9 +229,8 @@ AbstractController::isBlocked(Addr addr)
return (m_block_map.count(addr) > 0);
}
-BaseMasterPort &
-AbstractController::getMasterPort(const std::string &if_name,
- PortID idx)
+Port &
+AbstractController::getPort(const std::string &if_name, PortID idx)
{
return memoryPort;
}
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 35cd3d2a5..5e39a28d2 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -126,8 +126,8 @@ class AbstractController : public MemObject, public Consumer
virtual void initNetQueues() = 0;
/** A function used to return the port associated with this bus object. */
- BaseMasterPort& getMasterPort(const std::string& if_name,
- PortID idx = InvalidPortID);
+ Port &getPort(const std::string &if_name,
+ PortID idx=InvalidPortID);
void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency);
void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency,