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Diffstat (limited to 'src/mem/ruby/structures/Cache.py')
| -rw-r--r-- | src/mem/ruby/structures/Cache.py | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/src/mem/ruby/structures/Cache.py b/src/mem/ruby/structures/Cache.py new file mode 100644 index 000000000..14a359233 --- /dev/null +++ b/src/mem/ruby/structures/Cache.py @@ -0,0 +1,49 @@ +# Copyright (c) 2009 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Steve Reinhardt +# Brad Beckmann + +from m5.params import * +from m5.SimObject import SimObject +from Controller import RubyController + +class RubyCache(SimObject): + type = 'RubyCache' + cxx_class = 'CacheMemory' + cxx_header = "mem/ruby/structures/CacheMemory.hh" + size = Param.MemorySize("capacity in bytes"); + latency = Param.Cycles(""); + assoc = Param.Int(""); + replacement_policy = Param.String("PSEUDO_LRU", ""); + start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line"); + is_icache = Param.Bool(False, "is instruction only cache"); + + dataArrayBanks = Param.Int(1, "Number of banks for the data array") + tagArrayBanks = Param.Int(1, "Number of banks for the tag array") + dataAccessLatency = Param.Cycles(1, "cycles for a data array access") + tagAccessLatency = Param.Cycles(1, "cycles for a tag array access") + resourceStalls = Param.Bool(False, "stall if there is a resource failure") |