summaryrefslogtreecommitdiff
path: root/src/mem/ruby/structures/CacheMemory.hh
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem/ruby/structures/CacheMemory.hh')
-rw-r--r--src/mem/ruby/structures/CacheMemory.hh5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
index 08551ab87..6c719cb4f 100644
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -107,6 +107,11 @@ class CacheMemory : public SimObject
// Set this address to most recently used
void setMRU(Addr address);
+ // Functions for locking and unlocking cache lines corresponding to the
+ // provided address. These are required for supporting atomic memory
+ // accesses. These are to be used when only the address of the cache entry
+ // is available. In case the entry itself is available. use the functions
+ // provided by the AbstractCacheEntry class.
void setLocked (Addr addr, int context);
void clearLocked (Addr addr);
bool isLocked (Addr addr, int context);