diff options
Diffstat (limited to 'src/mem/ruby/structures')
| -rw-r--r-- | src/mem/ruby/structures/CacheMemory.cc | 82 | ||||
| -rw-r--r-- | src/mem/ruby/structures/CacheMemory.hh | 46 | ||||
| -rw-r--r-- | src/mem/ruby/structures/DirectoryMemory.cc | 31 | ||||
| -rw-r--r-- | src/mem/ruby/structures/DirectoryMemory.hh | 19 | ||||
| -rw-r--r-- | src/mem/ruby/structures/MemoryNode.hh | 6 | ||||
| -rw-r--r-- | src/mem/ruby/structures/PerfectCacheMemory.hh | 55 | ||||
| -rw-r--r-- | src/mem/ruby/structures/PersistentTable.cc | 36 | ||||
| -rw-r--r-- | src/mem/ruby/structures/PersistentTable.hh | 20 | ||||
| -rw-r--r-- | src/mem/ruby/structures/Prefetcher.cc | 78 | ||||
| -rw-r--r-- | src/mem/ruby/structures/Prefetcher.hh | 34 | ||||
| -rw-r--r-- | src/mem/ruby/structures/RubyMemoryControl.cc | 12 | ||||
| -rw-r--r-- | src/mem/ruby/structures/RubyMemoryControl.hh | 8 | ||||
| -rw-r--r-- | src/mem/ruby/structures/TBETable.hh | 20 | ||||
| -rw-r--r-- | src/mem/ruby/structures/TimerTable.cc | 12 | ||||
| -rw-r--r-- | src/mem/ruby/structures/TimerTable.hh | 14 |
15 files changed, 234 insertions, 239 deletions
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc index 64a8e9e8a..7eba450c1 100644 --- a/src/mem/ruby/structures/CacheMemory.cc +++ b/src/mem/ruby/structures/CacheMemory.cc @@ -99,21 +99,21 @@ CacheMemory::~CacheMemory() // convert a Address to its location in the cache int64 -CacheMemory::addressToCacheSet(const Address& address) const +CacheMemory::addressToCacheSet(Addr address) const { - assert(address == line_address(address)); - return address.bitSelect(m_start_index_bit, - m_start_index_bit + m_cache_num_set_bits - 1); + assert(address == makeLineAddress(address)); + return bitSelect(address, m_start_index_bit, + m_start_index_bit + m_cache_num_set_bits - 1); } // Given a cache index: returns the index of the tag in a set. // returns -1 if the tag is not found. int -CacheMemory::findTagInSet(int64 cacheSet, const Address& tag) const +CacheMemory::findTagInSet(int64 cacheSet, Addr tag) const { - assert(tag == line_address(tag)); + assert(tag == makeLineAddress(tag)); // search the set for the tags - m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag); + m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag); if (it != m_tag_index.end()) if (m_cache[cacheSet][it->second]->m_Permission != AccessPermission_NotPresent) @@ -125,11 +125,11 @@ CacheMemory::findTagInSet(int64 cacheSet, const Address& tag) const // returns -1 if the tag is not found. int CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet, - const Address& tag) const + Addr tag) const { - assert(tag == line_address(tag)); + assert(tag == makeLineAddress(tag)); // search the set for the tags - m5::hash_map<Address, int>::const_iterator it = m_tag_index.find(tag); + m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag); if (it != m_tag_index.end()) return it->second; return -1; // Not found @@ -138,10 +138,10 @@ CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet, // Given an unique cache block identifier (idx): return the valid address // stored by the cache block. If the block is invalid/notpresent, the // function returns the 0 address -Address +Addr CacheMemory::getAddressAtIdx(int idx) const { - Address tmp(0); + Addr tmp(0); int set = idx / m_cache_assoc; assert(set < m_cache_num_sets); @@ -159,10 +159,10 @@ CacheMemory::getAddressAtIdx(int idx) const } bool -CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type, +CacheMemory::tryCacheAccess(Addr address, RubyRequestType type, DataBlock*& data_ptr) { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); DPRINTF(RubyCache, "address: %s\n", address); int64 cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); @@ -186,10 +186,10 @@ CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type, } bool -CacheMemory::testCacheAccess(const Address& address, RubyRequestType type, +CacheMemory::testCacheAccess(Addr address, RubyRequestType type, DataBlock*& data_ptr) { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); DPRINTF(RubyCache, "address: %s\n", address); int64 cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); @@ -210,9 +210,9 @@ CacheMemory::testCacheAccess(const Address& address, RubyRequestType type, // tests to see if an address is present in the cache bool -CacheMemory::isTagPresent(const Address& address) const +CacheMemory::isTagPresent(Addr address) const { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); int64 cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); @@ -229,9 +229,9 @@ CacheMemory::isTagPresent(const Address& address) const // a) a tag match on this address or there is // b) an unused line in the same cache "way" bool -CacheMemory::cacheAvail(const Address& address) const +CacheMemory::cacheAvail(Addr address) const { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); int64 cacheSet = addressToCacheSet(address); @@ -251,9 +251,9 @@ CacheMemory::cacheAvail(const Address& address) const } AbstractCacheEntry* -CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry, bool touch) +CacheMemory::allocate(Addr address, AbstractCacheEntry* entry, bool touch) { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); assert(!isTagPresent(address)); assert(cacheAvail(address)); DPRINTF(RubyCache, "address: %s\n", address); @@ -282,9 +282,9 @@ CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry, bool to } void -CacheMemory::deallocate(const Address& address) +CacheMemory::deallocate(Addr address) { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); assert(isTagPresent(address)); DPRINTF(RubyCache, "address: %s\n", address); int64 cacheSet = addressToCacheSet(address); @@ -297,10 +297,10 @@ CacheMemory::deallocate(const Address& address) } // Returns with the physical address of the conflicting cache line -Address -CacheMemory::cacheProbe(const Address& address) const +Addr +CacheMemory::cacheProbe(Addr address) const { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); assert(!cacheAvail(address)); int64 cacheSet = addressToCacheSet(address); @@ -310,9 +310,9 @@ CacheMemory::cacheProbe(const Address& address) const // looks an address up in the cache AbstractCacheEntry* -CacheMemory::lookup(const Address& address) +CacheMemory::lookup(Addr address) { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); int64 cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if(loc == -1) return NULL; @@ -321,9 +321,9 @@ CacheMemory::lookup(const Address& address) // looks an address up in the cache const AbstractCacheEntry* -CacheMemory::lookup(const Address& address) const +CacheMemory::lookup(Addr address) const { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); int64 cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if(loc == -1) return NULL; @@ -332,7 +332,7 @@ CacheMemory::lookup(const Address& address) const // Sets the most recently used bit for a cache block void -CacheMemory::setMRU(const Address& address) +CacheMemory::setMRU(Addr address) { int64 cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); @@ -364,7 +364,7 @@ CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const } if (request_type != RubyRequestType_NULL) { - tr->addRecord(cntrl, m_cache[i][j]->m_Address.getAddress(), + tr->addRecord(cntrl, m_cache[i][j]->m_Address, 0, request_type, m_replacementPolicy_ptr->getLastAccess(i, j), m_cache[i][j]->getDataBlk()); @@ -406,10 +406,10 @@ CacheMemory::printData(ostream& out) const } void -CacheMemory::setLocked(const Address& address, int context) +CacheMemory::setLocked(Addr address, int context) { DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context); - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); int64 cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); assert(loc != -1); @@ -417,10 +417,10 @@ CacheMemory::setLocked(const Address& address, int context) } void -CacheMemory::clearLocked(const Address& address) +CacheMemory::clearLocked(Addr address) { DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address); - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); int64 cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); assert(loc != -1); @@ -428,9 +428,9 @@ CacheMemory::clearLocked(const Address& address) } bool -CacheMemory::isLocked(const Address& address, int context) +CacheMemory::isLocked(Addr address, int context) { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); int64 cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); assert(loc != -1); @@ -531,7 +531,7 @@ CacheMemory::regStats() // assumption: SLICC generated files will only call this function // once **all** resources are granted void -CacheMemory::recordRequestType(CacheRequestType requestType, Address addr) +CacheMemory::recordRequestType(CacheRequestType requestType, Addr addr) { DPRINTF(RubyStats, "Recorded statistic: %s\n", CacheRequestType_to_string(requestType)); @@ -563,7 +563,7 @@ CacheMemory::recordRequestType(CacheRequestType requestType, Address addr) } bool -CacheMemory::checkResourceAvailable(CacheResourceType res, Address addr) +CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr) { if (!m_resource_stalls) { return true; diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh index 792d8fd93..08551ab87 100644 --- a/src/mem/ruby/structures/CacheMemory.hh +++ b/src/mem/ruby/structures/CacheMemory.hh @@ -58,43 +58,42 @@ class CacheMemory : public SimObject // Public Methods // perform a cache access and see if we hit or not. Return true on a hit. - bool tryCacheAccess(const Address& address, RubyRequestType type, + bool tryCacheAccess(Addr address, RubyRequestType type, DataBlock*& data_ptr); // similar to above, but doesn't require full access check - bool testCacheAccess(const Address& address, RubyRequestType type, + bool testCacheAccess(Addr address, RubyRequestType type, DataBlock*& data_ptr); // tests to see if an address is present in the cache - bool isTagPresent(const Address& address) const; + bool isTagPresent(Addr address) const; // Returns true if there is: // a) a tag match on this address or there is // b) an unused line in the same cache "way" - bool cacheAvail(const Address& address) const; + bool cacheAvail(Addr address) const; // find an unused entry and sets the tag appropriate for the address - AbstractCacheEntry* allocate(const Address& address, + AbstractCacheEntry* allocate(Addr address, AbstractCacheEntry* new_entry, bool touch); - AbstractCacheEntry* allocate(const Address& address, - AbstractCacheEntry* new_entry) + AbstractCacheEntry* allocate(Addr address, AbstractCacheEntry* new_entry) { return allocate(address, new_entry, true); } - void allocateVoid(const Address& address, AbstractCacheEntry* new_entry) + void allocateVoid(Addr address, AbstractCacheEntry* new_entry) { allocate(address, new_entry, true); } // Explicitly free up this address - void deallocate(const Address& address); + void deallocate(Addr address); // Returns with the physical address of the conflicting cache line - Address cacheProbe(const Address& address) const; + Addr cacheProbe(Addr address) const; // looks an address up in the cache - AbstractCacheEntry* lookup(const Address& address); - const AbstractCacheEntry* lookup(const Address& address) const; + AbstractCacheEntry* lookup(Addr address); + const AbstractCacheEntry* lookup(Addr address) const; Cycles getTagLatency() const { return tagArray.getLatency(); } Cycles getDataLatency() const { return dataArray.getLatency(); } @@ -106,19 +105,19 @@ class CacheMemory : public SimObject void recordCacheContents(int cntrl, CacheRecorder* tr) const; // Set this address to most recently used - void setMRU(const Address& address); + void setMRU(Addr address); - void setLocked (const Address& addr, int context); - void clearLocked (const Address& addr); - bool isLocked (const Address& addr, int context); + void setLocked (Addr addr, int context); + void clearLocked (Addr addr); + bool isLocked (Addr addr, int context); // Print cache contents void print(std::ostream& out) const; void printData(std::ostream& out) const; void regStats(); - bool checkResourceAvailable(CacheResourceType res, Address addr); - void recordRequestType(CacheRequestType requestType, Address addr); + bool checkResourceAvailable(CacheResourceType res, Addr addr); + void recordRequestType(CacheRequestType requestType, Addr addr); public: Stats::Scalar m_demand_hits; @@ -141,17 +140,16 @@ class CacheMemory : public SimObject int getCacheSize() const { return m_cache_size; } int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; } - Address getAddressAtIdx(int idx) const; + Addr getAddressAtIdx(int idx) const; private: // convert a Address to its location in the cache - int64 addressToCacheSet(const Address& address) const; + int64 addressToCacheSet(Addr address) const; // Given a cache tag: returns the index of the tag in a set. // returns -1 if the tag is not found. - int findTagInSet(int64 line, const Address& tag) const; - int findTagInSetIgnorePermissions(int64 cacheSet, - const Address& tag) const; + int findTagInSet(int64 line, Addr tag) const; + int findTagInSetIgnorePermissions(int64 cacheSet, Addr tag) const; // Private copy constructor and assignment operator CacheMemory(const CacheMemory& obj); @@ -163,7 +161,7 @@ class CacheMemory : public SimObject // The first index is the # of cache lines. // The second index is the the amount associativity. - m5::hash_map<Address, int> m_tag_index; + m5::hash_map<Addr, int> m_tag_index; std::vector<std::vector<AbstractCacheEntry*> > m_cache; AbstractReplacementPolicy *m_replacementPolicy_ptr; diff --git a/src/mem/ruby/structures/DirectoryMemory.cc b/src/mem/ruby/structures/DirectoryMemory.cc index 04849e31f..b840349e1 100644 --- a/src/mem/ruby/structures/DirectoryMemory.cc +++ b/src/mem/ruby/structures/DirectoryMemory.cc @@ -71,7 +71,7 @@ DirectoryMemory::init() DirectoryMemory::~DirectoryMemory() { // free up all the directory entries - for (uint64 i = 0; i < m_num_entries; i++) { + for (uint64_t i = 0; i < m_num_entries; i++) { if (m_entries[i] != NULL) { delete m_entries[i]; } @@ -79,40 +79,41 @@ DirectoryMemory::~DirectoryMemory() delete [] m_entries; } -uint64 -DirectoryMemory::mapAddressToDirectoryVersion(PhysAddress address) +uint64_t +DirectoryMemory::mapAddressToDirectoryVersion(Addr address) { if (m_num_directories_bits == 0) return 0; - uint64 ret = address.bitSelect(m_numa_high_bit - m_num_directories_bits + 1, - m_numa_high_bit); + uint64_t ret = bitSelect(address, + m_numa_high_bit - m_num_directories_bits + 1, + m_numa_high_bit); return ret; } bool -DirectoryMemory::isPresent(PhysAddress address) +DirectoryMemory::isPresent(Addr address) { bool ret = (mapAddressToDirectoryVersion(address) == m_version); return ret; } -uint64 -DirectoryMemory::mapAddressToLocalIdx(PhysAddress address) +uint64_t +DirectoryMemory::mapAddressToLocalIdx(Addr address) { - uint64 ret; + uint64_t ret; if (m_num_directories_bits > 0) { - ret = address.bitRemove(m_numa_high_bit - m_num_directories_bits + 1, - m_numa_high_bit); + ret = bitRemove(address, m_numa_high_bit - m_num_directories_bits + 1, + m_numa_high_bit); } else { - ret = address.getAddress(); + ret = address; } return ret >> (RubySystem::getBlockSizeBits()); } AbstractEntry* -DirectoryMemory::lookup(PhysAddress address) +DirectoryMemory::lookup(Addr address) { assert(isPresent(address)); DPRINTF(RubyCache, "Looking up address: %s\n", address); @@ -123,10 +124,10 @@ DirectoryMemory::lookup(PhysAddress address) } AbstractEntry* -DirectoryMemory::allocate(const PhysAddress& address, AbstractEntry* entry) +DirectoryMemory::allocate(Addr address, AbstractEntry *entry) { assert(isPresent(address)); - uint64 idx; + uint64_t idx; DPRINTF(RubyCache, "Looking up address: %s\n", address); idx = mapAddressToLocalIdx(address); diff --git a/src/mem/ruby/structures/DirectoryMemory.hh b/src/mem/ruby/structures/DirectoryMemory.hh index b75e6ab72..a549366d0 100644 --- a/src/mem/ruby/structures/DirectoryMemory.hh +++ b/src/mem/ruby/structures/DirectoryMemory.hh @@ -47,15 +47,14 @@ class DirectoryMemory : public SimObject void init(); - uint64 mapAddressToLocalIdx(PhysAddress address); - static uint64 mapAddressToDirectoryVersion(PhysAddress address); + uint64_t mapAddressToLocalIdx(Addr address); + static uint64_t mapAddressToDirectoryVersion(Addr address); - uint64 getSize() { return m_size_bytes; } + uint64_t getSize() { return m_size_bytes; } - bool isPresent(PhysAddress address); - AbstractEntry* lookup(PhysAddress address); - AbstractEntry* allocate(const PhysAddress& address, - AbstractEntry* new_entry); + bool isPresent(Addr address); + AbstractEntry *lookup(Addr address); + AbstractEntry *allocate(Addr address, AbstractEntry* new_entry); void print(std::ostream& out) const; void recordRequestType(DirectoryRequestType requestType); @@ -70,9 +69,9 @@ class DirectoryMemory : public SimObject AbstractEntry **m_entries; // int m_size; // # of memory module blocks this directory is // responsible for - uint64 m_size_bytes; - uint64 m_size_bits; - uint64 m_num_entries; + uint64_t m_size_bytes; + uint64_t m_size_bits; + uint64_t m_num_entries; int m_version; static int m_num_directories; diff --git a/src/mem/ruby/structures/MemoryNode.hh b/src/mem/ruby/structures/MemoryNode.hh index b48f64704..558457e23 100644 --- a/src/mem/ruby/structures/MemoryNode.hh +++ b/src/mem/ruby/structures/MemoryNode.hh @@ -48,7 +48,7 @@ class MemoryNode public: // old constructor MemoryNode(const Cycles& time, int counter, const PacketPtr p, - const physical_address_t addr, const bool is_mem_read) + Addr addr, const bool is_mem_read) : m_time(time), pkt(p) { m_msg_counter = counter; @@ -59,7 +59,7 @@ class MemoryNode // new constructor MemoryNode(const Cycles& time, const PacketPtr p, - const physical_address_t addr, const bool is_mem_read, + Addr addr, const bool is_mem_read, const bool is_dirty_wb) : m_time(time), pkt(p) { @@ -74,7 +74,7 @@ class MemoryNode Cycles m_time; int m_msg_counter; PacketPtr pkt; - physical_address_t m_addr; + Addr m_addr; bool m_is_mem_read; bool m_is_dirty_wb; }; diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh b/src/mem/ruby/structures/PerfectCacheMemory.hh index 413a0f471..2b8b87628 100644 --- a/src/mem/ruby/structures/PerfectCacheMemory.hh +++ b/src/mem/ruby/structures/PerfectCacheMemory.hh @@ -55,28 +55,28 @@ class PerfectCacheMemory PerfectCacheMemory(); // tests to see if an address is present in the cache - bool isTagPresent(const Address& address) const; + bool isTagPresent(Addr address) const; // Returns true if there is: // a) a tag match on this address or there is // b) an Invalid line in the same cache "way" - bool cacheAvail(const Address& address) const; + bool cacheAvail(Addr address) const; // find an Invalid entry and sets the tag appropriate for the address - void allocate(const Address& address); + void allocate(Addr address); - void deallocate(const Address& address); + void deallocate(Addr address); // Returns with the physical address of the conflicting cache line - Address cacheProbe(const Address& newAddress) const; + Addr cacheProbe(Addr newAddress) const; // looks an address up in the cache - ENTRY* lookup(const Address& address); - const ENTRY* lookup(const Address& address) const; + ENTRY* lookup(Addr address); + const ENTRY* lookup(Addr address) const; // Get/Set permission of cache block - AccessPermission getPermission(const Address& address) const; - void changePermission(const Address& address, AccessPermission new_perm); + AccessPermission getPermission(Addr address) const; + void changePermission(Addr address, AccessPermission new_perm); // Print cache contents void print(std::ostream& out) const; @@ -87,7 +87,7 @@ class PerfectCacheMemory PerfectCacheMemory& operator=(const PerfectCacheMemory& obj); // Data Members (m_prefix) - m5::hash_map<Address, PerfectCacheLineState<ENTRY> > m_map; + m5::hash_map<Addr, PerfectCacheLineState<ENTRY> > m_map; }; template<class ENTRY> @@ -108,14 +108,14 @@ PerfectCacheMemory<ENTRY>::PerfectCacheMemory() // tests to see if an address is present in the cache template<class ENTRY> inline bool -PerfectCacheMemory<ENTRY>::isTagPresent(const Address& address) const +PerfectCacheMemory<ENTRY>::isTagPresent(Addr address) const { - return m_map.count(line_address(address)) > 0; + return m_map.count(makeLineAddress(address)) > 0; } template<class ENTRY> inline bool -PerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const +PerfectCacheMemory<ENTRY>::cacheAvail(Addr address) const { return true; } @@ -124,26 +124,26 @@ PerfectCacheMemory<ENTRY>::cacheAvail(const Address& address) const // appropriate for the address template<class ENTRY> inline void -PerfectCacheMemory<ENTRY>::allocate(const Address& address) +PerfectCacheMemory<ENTRY>::allocate(Addr address) { PerfectCacheLineState<ENTRY> line_state; line_state.m_permission = AccessPermission_Invalid; line_state.m_entry = ENTRY(); - m_map[line_address(address)] = line_state; + m_map[makeLineAddress(address)] = line_state; } // deallocate entry template<class ENTRY> inline void -PerfectCacheMemory<ENTRY>::deallocate(const Address& address) +PerfectCacheMemory<ENTRY>::deallocate(Addr address) { - m_map.erase(line_address(address)); + m_map.erase(makeLineAddress(address)); } // Returns with the physical address of the conflicting cache line template<class ENTRY> -inline Address -PerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const +inline Addr +PerfectCacheMemory<ENTRY>::cacheProbe(Addr newAddress) const { panic("cacheProbe called in perfect cache"); return newAddress; @@ -152,33 +152,32 @@ PerfectCacheMemory<ENTRY>::cacheProbe(const Address& newAddress) const // looks an address up in the cache template<class ENTRY> inline ENTRY* -PerfectCacheMemory<ENTRY>::lookup(const Address& address) +PerfectCacheMemory<ENTRY>::lookup(Addr address) { - return &m_map[line_address(address)].m_entry; + return &m_map[makeLineAddress(address)].m_entry; } // looks an address up in the cache template<class ENTRY> inline const ENTRY* -PerfectCacheMemory<ENTRY>::lookup(const Address& address) const +PerfectCacheMemory<ENTRY>::lookup(Addr address) const { - return &m_map[line_address(address)].m_entry; + return &m_map[makeLineAddress(address)].m_entry; } template<class ENTRY> inline AccessPermission -PerfectCacheMemory<ENTRY>::getPermission(const Address& address) const +PerfectCacheMemory<ENTRY>::getPermission(Addr address) const { - return m_map[line_address(address)].m_permission; + return m_map[makeLineAddress(address)].m_permission; } template<class ENTRY> inline void -PerfectCacheMemory<ENTRY>::changePermission(const Address& address, +PerfectCacheMemory<ENTRY>::changePermission(Addr address, AccessPermission new_perm) { - Address line_address = address; - line_address.makeLineAddress(); + Addr line_address = makeLineAddress(address); PerfectCacheLineState<ENTRY>& line_state = m_map[line_address]; line_state.m_permission = new_perm; } diff --git a/src/mem/ruby/structures/PersistentTable.cc b/src/mem/ruby/structures/PersistentTable.cc index 57b06946e..1e4e0f555 100644 --- a/src/mem/ruby/structures/PersistentTable.cc +++ b/src/mem/ruby/structures/PersistentTable.cc @@ -47,7 +47,7 @@ PersistentTable::~PersistentTable() } void -PersistentTable::persistentRequestLock(const Address& address, +PersistentTable::persistentRequestLock(Addr address, MachineID locker, AccessType type) { @@ -59,7 +59,7 @@ PersistentTable::persistentRequestLock(const Address& address, MachineID locker = (MachineID) persistent_randomize[llocker]; #endif - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); static const PersistentTableEntry dflt; pair<AddressMap::iterator, bool> r = @@ -82,7 +82,7 @@ PersistentTable::persistentRequestLock(const Address& address, } void -PersistentTable::persistentRequestUnlock(const Address& address, +PersistentTable::persistentRequestUnlock(Addr address, MachineID unlocker) { #if 0 @@ -93,7 +93,7 @@ PersistentTable::persistentRequestUnlock(const Address& address, MachineID unlocker = (MachineID) persistent_randomize[uunlocker]; #endif - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); assert(m_map.count(address)); PersistentTableEntry& entry = m_map[address]; @@ -115,10 +115,10 @@ PersistentTable::persistentRequestUnlock(const Address& address, } bool -PersistentTable::okToIssueStarving(const Address& address, +PersistentTable::okToIssueStarving(Addr address, MachineID machId) const { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); AddressMap::const_iterator i = m_map.find(address); if (i == m_map.end()) { @@ -138,9 +138,9 @@ PersistentTable::okToIssueStarving(const Address& address, } MachineID -PersistentTable::findSmallest(const Address& address) const +PersistentTable::findSmallest(Addr address) const { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); AddressMap::const_iterator i = m_map.find(address); assert(i != m_map.end()); const PersistentTableEntry& entry = i->second; @@ -148,9 +148,9 @@ PersistentTable::findSmallest(const Address& address) const } AccessType -PersistentTable::typeOfSmallest(const Address& address) const +PersistentTable::typeOfSmallest(Addr address) const { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); AddressMap::const_iterator i = m_map.find(address); assert(i != m_map.end()); const PersistentTableEntry& entry = i->second; @@ -163,9 +163,9 @@ PersistentTable::typeOfSmallest(const Address& address) const } void -PersistentTable::markEntries(const Address& address) +PersistentTable::markEntries(Addr address) { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); AddressMap::iterator i = m_map.find(address); if (i == m_map.end()) return; @@ -180,18 +180,18 @@ PersistentTable::markEntries(const Address& address) } bool -PersistentTable::isLocked(const Address& address) const +PersistentTable::isLocked(Addr address) const { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); // If an entry is present, it must be locked return m_map.count(address) > 0; } int -PersistentTable::countStarvingForAddress(const Address& address) const +PersistentTable::countStarvingForAddress(Addr address) const { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); AddressMap::const_iterator i = m_map.find(address); if (i == m_map.end()) return 0; @@ -201,9 +201,9 @@ PersistentTable::countStarvingForAddress(const Address& address) const } int -PersistentTable::countReadStarvingForAddress(const Address& address) const +PersistentTable::countReadStarvingForAddress(Addr address) const { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); AddressMap::const_iterator i = m_map.find(address); if (i == m_map.end()) return 0; diff --git a/src/mem/ruby/structures/PersistentTable.hh b/src/mem/ruby/structures/PersistentTable.hh index 7e10b328c..a4604fce8 100644 --- a/src/mem/ruby/structures/PersistentTable.hh +++ b/src/mem/ruby/structures/PersistentTable.hh @@ -58,16 +58,16 @@ class PersistentTable ~PersistentTable(); // Public Methods - void persistentRequestLock(const Address& address, MachineID locker, + void persistentRequestLock(Addr address, MachineID locker, AccessType type); - void persistentRequestUnlock(const Address& address, MachineID unlocker); - bool okToIssueStarving(const Address& address, MachineID machID) const; - MachineID findSmallest(const Address& address) const; - AccessType typeOfSmallest(const Address& address) const; - void markEntries(const Address& address); - bool isLocked(const Address& addr) const; - int countStarvingForAddress(const Address& addr) const; - int countReadStarvingForAddress(const Address& addr) const; + void persistentRequestUnlock(Addr address, MachineID unlocker); + bool okToIssueStarving(Addr address, MachineID machID) const; + MachineID findSmallest(Addr address) const; + AccessType typeOfSmallest(Addr address) const; + void markEntries(Addr address); + bool isLocked(Addr addr) const; + int countStarvingForAddress(Addr addr) const; + int countReadStarvingForAddress(Addr addr) const; void print(std::ostream& out) const; @@ -77,7 +77,7 @@ class PersistentTable PersistentTable& operator=(const PersistentTable& obj); // Data Members (m_prefix) - typedef m5::hash_map<Address, PersistentTableEntry> AddressMap; + typedef m5::hash_map<Addr, PersistentTableEntry> AddressMap; AddressMap m_map; }; diff --git a/src/mem/ruby/structures/Prefetcher.cc b/src/mem/ruby/structures/Prefetcher.cc index 306174c2c..fbf027bef 100644 --- a/src/mem/ruby/structures/Prefetcher.cc +++ b/src/mem/ruby/structures/Prefetcher.cc @@ -42,9 +42,9 @@ Prefetcher::Prefetcher(const Params *p) m_array(p->num_streams), m_train_misses(p->train_misses), m_num_startup_pfs(p->num_startup_pfs), m_num_unit_filters(p->unit_filter), m_num_nonunit_filters(p->nonunit_filter), - m_unit_filter(p->unit_filter, Address(0)), - m_negative_filter(p->unit_filter, Address(0)), - m_nonunit_filter(p->nonunit_filter, Address(0)), + m_unit_filter(p->unit_filter, 0), + m_negative_filter(p->unit_filter, 0), + m_nonunit_filter(p->nonunit_filter, 0), m_prefetch_cross_pages(p->cross_page), m_page_shift(p->sys->getPageShift()) { @@ -133,10 +133,10 @@ Prefetcher::regStats() } void -Prefetcher::observeMiss(const Address& address, const RubyRequestType& type) +Prefetcher::observeMiss(Addr address, const RubyRequestType& type) { DPRINTF(RubyPrefetcher, "Observed miss for %s\n", address); - Address line_addr = line_address(address); + Addr line_addr = makeLineAddress(address); numMissObserved++; // check to see if we have already issued a prefetch for this block @@ -201,7 +201,7 @@ Prefetcher::observeMiss(const Address& address, const RubyRequestType& type) } void -Prefetcher::observePfMiss(const Address& address) +Prefetcher::observePfMiss(Addr address) { numPartialHits++; DPRINTF(RubyPrefetcher, "Observed partial hit for %s\n", address); @@ -209,7 +209,7 @@ Prefetcher::observePfMiss(const Address& address) } void -Prefetcher::observePfHit(const Address& address) +Prefetcher::observePfHit(Addr address) { numHits++; DPRINTF(RubyPrefetcher, "Observed hit for %s\n", address); @@ -217,7 +217,7 @@ Prefetcher::observePfHit(const Address& address) } void -Prefetcher::issueNextPrefetch(const Address &address, PrefetchEntry *stream) +Prefetcher::issueNextPrefetch(Addr address, PrefetchEntry *stream) { // get our corresponding stream fetcher if (stream == NULL) { @@ -232,9 +232,9 @@ Prefetcher::issueNextPrefetch(const Address &address, PrefetchEntry *stream) } // extend this prefetching stream by 1 (or more) - Address page_addr = pageAddress(stream->m_address); - Address line_addr = next_stride_address(stream->m_address, - stream->m_stride); + Addr page_addr = pageAddress(stream->m_address); + Addr line_addr = makeNextStrideAddress(stream->m_address, + stream->m_stride); // possibly stop prefetching at page boundaries if (page_addr != pageAddress(line_addr)) { @@ -276,33 +276,32 @@ Prefetcher::getLRUindex(void) void Prefetcher::clearNonunitEntry(uint32_t index) { - m_nonunit_filter[index].setAddress(0); + m_nonunit_filter[index] = 0; m_nonunit_stride[index] = 0; m_nonunit_hit[index] = 0; } void -Prefetcher::initializeStream(const Address& address, int stride, +Prefetcher::initializeStream(Addr address, int stride, uint32_t index, const RubyRequestType& type) { numAllocatedStreams++; // initialize the stream prefetcher PrefetchEntry *mystream = &(m_array[index]); - mystream->m_address = line_address(address); + mystream->m_address = makeLineAddress(address); mystream->m_stride = stride; mystream->m_use_time = m_controller->curCycle(); mystream->m_is_valid = true; mystream->m_type = type; // create a number of initial prefetches for this stream - Address page_addr = pageAddress(mystream->m_address); - Address line_addr = line_address(mystream->m_address); - Address prev_addr = line_addr; + Addr page_addr = pageAddress(mystream->m_address); + Addr line_addr = makeLineAddress(mystream->m_address); // insert a number of prefetches into the prefetch table for (int k = 0; k < m_num_startup_pfs; k++) { - line_addr = next_stride_address(line_addr, stride); + line_addr = makeNextStrideAddress(line_addr, stride); // possibly stop prefetching at page boundaries if (page_addr != pageAddress(line_addr)) { numPagesCrossed++; @@ -317,7 +316,6 @@ Prefetcher::initializeStream(const Address& address, int stride, numPrefetchRequested++; DPRINTF(RubyPrefetcher, "Requesting prefetch for %s\n", line_addr); m_controller->enqueuePrefetch(line_addr, m_array[index].m_type); - prev_addr = line_addr; } // update the address to be the last address prefetched @@ -325,14 +323,14 @@ Prefetcher::initializeStream(const Address& address, int stride, } PrefetchEntry * -Prefetcher::getPrefetchEntry(const Address &address, uint32_t &index) +Prefetcher::getPrefetchEntry(Addr address, uint32_t &index) { // search all streams for a match for (int i = 0; i < m_num_streams; i++) { // search all the outstanding prefetches for this stream if (m_array[i].m_is_valid) { for (int j = 0; j < m_num_startup_pfs; j++) { - if (next_stride_address(m_array[i].m_address, + if (makeNextStrideAddress(m_array[i].m_address, -(m_array[i].m_stride*j)) == address) { return &(m_array[i]); } @@ -343,17 +341,17 @@ Prefetcher::getPrefetchEntry(const Address &address, uint32_t &index) } bool -Prefetcher::accessUnitFilter(std::vector<Address>& filter_table, - uint32_t *filter_hit, uint32_t &index, const Address &address, +Prefetcher::accessUnitFilter(std::vector<Addr>& filter_table, + uint32_t *filter_hit, uint32_t &index, Addr address, int stride, bool &alloc) { //reset the alloc flag alloc = false; - Address line_addr = line_address(address); + Addr line_addr = makeLineAddress(address); for (int i = 0; i < m_num_unit_filters; i++) { if (filter_table[i] == line_addr) { - filter_table[i] = next_stride_address(filter_table[i], stride); + filter_table[i] = makeNextStrideAddress(filter_table[i], stride); filter_hit[i]++; if (filter_hit[i] >= m_train_misses) { alloc = true; @@ -364,7 +362,7 @@ Prefetcher::accessUnitFilter(std::vector<Address>& filter_table, // enter this address in the table int local_index = index; - filter_table[local_index] = next_stride_address(line_addr, stride); + filter_table[local_index] = makeNextStrideAddress(line_addr, stride); filter_hit[local_index] = 0; local_index = local_index + 1; if (local_index >= m_num_unit_filters) { @@ -376,21 +374,21 @@ Prefetcher::accessUnitFilter(std::vector<Address>& filter_table, } bool -Prefetcher::accessNonunitFilter(const Address& address, int *stride, +Prefetcher::accessNonunitFilter(Addr address, int *stride, bool &alloc) { //reset the alloc flag alloc = false; /// look for non-unit strides based on a (user-defined) page size - Address page_addr = pageAddress(address); - Address line_addr = line_address(address); + Addr page_addr = pageAddress(address); + Addr line_addr = makeLineAddress(address); for (uint32_t i = 0; i < m_num_nonunit_filters; i++) { if (pageAddress(m_nonunit_filter[i]) == page_addr) { // hit in the non-unit filter // compute the actual stride (for this reference) - int delta = line_addr.getAddress() - m_nonunit_filter[i].getAddress(); + int delta = line_addr - m_nonunit_filter[i]; if (delta != 0) { // no zero stride prefetches @@ -400,17 +398,19 @@ Prefetcher::accessNonunitFilter(const Address& address, int *stride, // increment count (if > 2) allocate stream m_nonunit_hit[i]++; if (m_nonunit_hit[i] > m_train_misses) { - //This stride HAS to be the multiplicative constant of - //dataBlockBytes (bc next_stride_address is calculated based - //on this multiplicative constant!) - *stride = m_nonunit_stride[i]/RubySystem::getBlockSizeBytes(); + // This stride HAS to be the multiplicative constant of + // dataBlockBytes (bc makeNextStrideAddress is + // calculated based on this multiplicative constant!) + *stride = m_nonunit_stride[i] / + RubySystem::getBlockSizeBytes(); // clear this filter entry clearNonunitEntry(i); alloc = true; } } else { - // delta didn't match ... reset m_nonunit_hit count for this entry + // delta didn't match ... reset m_nonunit_hit count for + // this entry m_nonunit_hit[i] = 0; } @@ -469,10 +469,8 @@ Prefetcher::print(std::ostream& out) const } } -Address -Prefetcher::pageAddress(const Address& addr) const +Addr +Prefetcher::pageAddress(Addr addr) const { - Address temp = addr; - temp.maskLowOrderBits(m_page_shift); - return temp; + return maskLowOrderBits(addr, m_page_shift); } diff --git a/src/mem/ruby/structures/Prefetcher.hh b/src/mem/ruby/structures/Prefetcher.hh index 6ed945b9e..d5c3d4b58 100644 --- a/src/mem/ruby/structures/Prefetcher.hh +++ b/src/mem/ruby/structures/Prefetcher.hh @@ -26,8 +26,8 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#ifndef PREFETCHER_H -#define PREFETCHER_H +#ifndef __MEM_RUBY_STRUCTURES_PREFETCHER_HH__ +#define __MEM_RUBY_STRUCTURES_PREFETCHER_HH__ // Implements Power 4 like prefetching @@ -58,7 +58,7 @@ class PrefetchEntry } //! The base address for the stream prefetch - Address m_address; + Addr m_address; //! stride distance to get next address from int m_stride; @@ -85,22 +85,22 @@ class Prefetcher : public SimObject Prefetcher(const Params *p); ~Prefetcher(); - void issueNextPrefetch(const Address &address, PrefetchEntry *stream); + void issueNextPrefetch(Addr address, PrefetchEntry *stream); /** * Implement the prefetch hit(miss) callback interface. * These functions are called by the cache when it hits(misses) * on a line with the line's prefetch bit set. If this address * hits in m_array we will continue prefetching the stream. */ - void observePfHit(const Address& address); - void observePfMiss(const Address& address); + void observePfHit(Addr address); + void observePfMiss(Addr address); /** * Observe a memory miss from the cache. * * @param address The physical address that missed out of the cache. */ - void observeMiss(const Address& address, const RubyRequestType& type); + void observeMiss(Addr address, const RubyRequestType& type); /** * Print out some statistics @@ -123,25 +123,25 @@ class Prefetcher : public SimObject void clearNonunitEntry(uint32_t index); //! allocate a new stream buffer at a specific index - void initializeStream(const Address& address, int stride, + void initializeStream(Addr address, int stride, uint32_t index, const RubyRequestType& type); //! get pointer to the matching stream entry, returns NULL if not found //! index holds the multiple of the stride this address is. - PrefetchEntry* getPrefetchEntry(const Address &address, + PrefetchEntry* getPrefetchEntry(Addr address, uint32_t &index); /// access a unit stride filter to determine if there is a hit - bool accessUnitFilter(std::vector<Address>& filter_table, - uint32_t *hit_table, uint32_t &index, const Address &address, + bool accessUnitFilter(std::vector<Addr>& filter_table, + uint32_t *hit_table, uint32_t &index, Addr address, int stride, bool &alloc); /// access a unit stride filter to determine if there is a hit - bool accessNonunitFilter(const Address& address, int *stride, + bool accessNonunitFilter(Addr address, int *stride, bool &alloc); /// determine the page aligned address - Address pageAddress(const Address& addr) const; + Addr pageAddress(Addr addr) const; //! number of prefetch streams available uint32_t m_num_streams; @@ -159,7 +159,7 @@ class Prefetcher : public SimObject /// a unit stride filter array: helps reduce BW requirement of /// prefetching - std::vector<Address> m_unit_filter; + std::vector<Addr> m_unit_filter; /// a round robin pointer into the unit filter group uint32_t m_unit_filter_index; //! An array used to count the of times particular filter entries @@ -168,7 +168,7 @@ class Prefetcher : public SimObject //! a negative nit stride filter array: helps reduce BW requirement //! of prefetching - std::vector<Address> m_negative_filter; + std::vector<Addr> m_negative_filter; /// a round robin pointer into the negative filter group uint32_t m_negative_filter_index; /// An array used to count the of times particular filter entries @@ -177,7 +177,7 @@ class Prefetcher : public SimObject /// a non-unit stride filter array: helps reduce BW requirement of /// prefetching - std::vector<Address> m_nonunit_filter; + std::vector<Addr> m_nonunit_filter; /// An array of strides (in # of cache lines) for the filter entries int *m_nonunit_stride; /// An array used to count the of times particular filter entries @@ -213,4 +213,4 @@ class Prefetcher : public SimObject Stats::Scalar numMissedPrefetchedBlocks; }; -#endif // PREFETCHER_H +#endif // __MEM_RUBY_STRUCTURES_PREFETCHER_HH__ diff --git a/src/mem/ruby/structures/RubyMemoryControl.cc b/src/mem/ruby/structures/RubyMemoryControl.cc index 9cf8673a2..0521aac06 100644 --- a/src/mem/ruby/structures/RubyMemoryControl.cc +++ b/src/mem/ruby/structures/RubyMemoryControl.cc @@ -289,7 +289,7 @@ bool RubyMemoryControl::recvTimingReq(PacketPtr pkt) { Cycles arrival_time = curCycle(); - physical_address_t addr = pkt->getAddr(); + Addr addr = pkt->getAddr(); bool is_mem_read = pkt->isRead(); access(pkt); @@ -306,7 +306,7 @@ RubyMemoryControl::enqueueMemRef(MemoryNode *memRef) { m_msg_counter++; memRef->m_msg_counter = m_msg_counter; - physical_address_t addr = memRef->m_addr; + Addr addr = memRef->m_addr; int bank = getBank(addr); m_profiler_ptr->profileMemReq(bank); @@ -343,7 +343,7 @@ RubyMemoryControl::enqueueToDirectory(MemoryNode *req, Cycles latency) // getBank returns an integer that is unique for each // bank across this memory controller. const int -RubyMemoryControl::getBank(const physical_address_t addr) const +RubyMemoryControl::getBank(const Addr addr) const { int dimm = (addr >> m_dimm_bit_0) & (m_dimms_per_channel - 1); int rank = (addr >> m_rank_bit_0) & (m_ranks_per_dimm - 1); @@ -354,7 +354,7 @@ RubyMemoryControl::getBank(const physical_address_t addr) const } const int -RubyMemoryControl::getRank(const physical_address_t addr) const +RubyMemoryControl::getRank(const Addr addr) const { int bank = getBank(addr); int rank = (bank / m_banks_per_rank); @@ -374,7 +374,7 @@ RubyMemoryControl::getRank(int bank) const // Not used! const int -RubyMemoryControl::getChannel(const physical_address_t addr) const +RubyMemoryControl::getChannel(const Addr addr) const { assert(false); return -1; @@ -382,7 +382,7 @@ RubyMemoryControl::getChannel(const physical_address_t addr) const // Not used! const int -RubyMemoryControl::getRow(const physical_address_t addr) const +RubyMemoryControl::getRow(const Addr addr) const { assert(false); return -1; diff --git a/src/mem/ruby/structures/RubyMemoryControl.hh b/src/mem/ruby/structures/RubyMemoryControl.hh index c7bebc447..c68a2da6c 100644 --- a/src/mem/ruby/structures/RubyMemoryControl.hh +++ b/src/mem/ruby/structures/RubyMemoryControl.hh @@ -75,12 +75,12 @@ class RubyMemoryControl : public AbstractMemory, public Consumer void print(std::ostream& out) const; void regStats(); - const int getBank(const physical_address_t addr) const; - const int getRank(const physical_address_t addr) const; + const int getBank(const Addr addr) const; + const int getRank(const Addr addr) const; // not used in Ruby memory controller - const int getChannel(const physical_address_t addr) const; - const int getRow(const physical_address_t addr) const; + const int getChannel(const Addr addr) const; + const int getRow(const Addr addr) const; //added by SS int getBanksPerRank() { return m_banks_per_rank; }; diff --git a/src/mem/ruby/structures/TBETable.hh b/src/mem/ruby/structures/TBETable.hh index a3282af7d..cbc51dae5 100644 --- a/src/mem/ruby/structures/TBETable.hh +++ b/src/mem/ruby/structures/TBETable.hh @@ -43,16 +43,16 @@ class TBETable { } - bool isPresent(const Address& address) const; - void allocate(const Address& address); - void deallocate(const Address& address); + bool isPresent(Addr address) const; + void allocate(Addr address); + void deallocate(Addr address); bool areNSlotsAvailable(int n) const { return (m_number_of_TBEs - m_map.size()) >= n; } - ENTRY* lookup(const Address& address); + ENTRY* lookup(Addr address); // Print cache contents void print(std::ostream& out) const; @@ -63,7 +63,7 @@ class TBETable TBETable& operator=(const TBETable& obj); // Data Members (m_prefix) - m5::hash_map<Address, ENTRY> m_map; + m5::hash_map<Addr, ENTRY> m_map; private: int m_number_of_TBEs; @@ -80,16 +80,16 @@ operator<<(std::ostream& out, const TBETable<ENTRY>& obj) template<class ENTRY> inline bool -TBETable<ENTRY>::isPresent(const Address& address) const +TBETable<ENTRY>::isPresent(Addr address) const { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); assert(m_map.size() <= m_number_of_TBEs); return !!m_map.count(address); } template<class ENTRY> inline void -TBETable<ENTRY>::allocate(const Address& address) +TBETable<ENTRY>::allocate(Addr address) { assert(!isPresent(address)); assert(m_map.size() < m_number_of_TBEs); @@ -98,7 +98,7 @@ TBETable<ENTRY>::allocate(const Address& address) template<class ENTRY> inline void -TBETable<ENTRY>::deallocate(const Address& address) +TBETable<ENTRY>::deallocate(Addr address) { assert(isPresent(address)); assert(m_map.size() > 0); @@ -108,7 +108,7 @@ TBETable<ENTRY>::deallocate(const Address& address) // looks an address up in the cache template<class ENTRY> inline ENTRY* -TBETable<ENTRY>::lookup(const Address& address) +TBETable<ENTRY>::lookup(Addr address) { if(m_map.find(address) != m_map.end()) return &(m_map.find(address)->second); return NULL; diff --git a/src/mem/ruby/structures/TimerTable.cc b/src/mem/ruby/structures/TimerTable.cc index d40ae2b79..7d0dd3c01 100644 --- a/src/mem/ruby/structures/TimerTable.cc +++ b/src/mem/ruby/structures/TimerTable.cc @@ -36,7 +36,7 @@ TimerTable::TimerTable() m_clockobj_ptr = NULL; m_next_valid = false; - m_next_address = Address(0); + m_next_address = 0; } bool @@ -52,7 +52,7 @@ TimerTable::isReady() const return (m_clockobj_ptr->curCycle() >= m_next_time); } -const Address& +Addr TimerTable::readyAddress() const { assert(isReady()); @@ -65,9 +65,9 @@ TimerTable::readyAddress() const } void -TimerTable::set(const Address& address, Cycles relative_latency) +TimerTable::set(Addr address, Cycles relative_latency) { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); assert(relative_latency > 0); assert(!m_map.count(address)); @@ -85,9 +85,9 @@ TimerTable::set(const Address& address, Cycles relative_latency) } void -TimerTable::unset(const Address& address) +TimerTable::unset(Addr address) { - assert(address == line_address(address)); + assert(address == makeLineAddress(address)); assert(m_map.count(address)); m_map.erase(address); diff --git a/src/mem/ruby/structures/TimerTable.hh b/src/mem/ruby/structures/TimerTable.hh index c5277818b..606201eb4 100644 --- a/src/mem/ruby/structures/TimerTable.hh +++ b/src/mem/ruby/structures/TimerTable.hh @@ -62,13 +62,13 @@ class TimerTable } bool isReady() const; - const Address& readyAddress() const; - bool isSet(const Address& address) const { return !!m_map.count(address); } - void set(const Address& address, Cycles relative_latency); - void set(const Address& address, uint64_t relative_latency) + Addr readyAddress() const; + bool isSet(Addr address) const { return !!m_map.count(address); } + void set(Addr address, Cycles relative_latency); + void set(Addr address, uint64_t relative_latency) { set(address, Cycles(relative_latency)); } - void unset(const Address& address); + void unset(Addr address); void print(std::ostream& out) const; private: @@ -82,11 +82,11 @@ class TimerTable // use a std::map for the address map as this container is sorted // and ensures a well-defined iteration order - typedef std::map<Address, Cycles> AddressMap; + typedef std::map<Addr, Cycles> AddressMap; AddressMap m_map; mutable bool m_next_valid; mutable Cycles m_next_time; // Only valid if m_next_valid is true - mutable Address m_next_address; // Only valid if m_next_valid is true + mutable Addr m_next_address; // Only valid if m_next_valid is true //! Object used for querying time. ClockedObject* m_clockobj_ptr; |