diff options
Diffstat (limited to 'src/mem/ruby/structures')
-rw-r--r-- | src/mem/ruby/structures/CacheMemory.cc | 4 | ||||
-rw-r--r-- | src/mem/ruby/structures/CacheMemory.hh | 4 | ||||
-rw-r--r-- | src/mem/ruby/structures/PerfectCacheMemory.hh | 5 | ||||
-rw-r--r-- | src/mem/ruby/structures/PersistentTable.hh | 4 | ||||
-rw-r--r-- | src/mem/ruby/structures/RubyMemoryControl.hh | 2 | ||||
-rw-r--r-- | src/mem/ruby/structures/TBETable.hh | 4 |
6 files changed, 12 insertions, 11 deletions
diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc index 6e4022ea6..a8a3ba949 100644 --- a/src/mem/ruby/structures/CacheMemory.cc +++ b/src/mem/ruby/structures/CacheMemory.cc @@ -113,7 +113,7 @@ CacheMemory::findTagInSet(int64_t cacheSet, Addr tag) const { assert(tag == makeLineAddress(tag)); // search the set for the tags - m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag); + auto it = m_tag_index.find(tag); if (it != m_tag_index.end()) if (m_cache[cacheSet][it->second]->m_Permission != AccessPermission_NotPresent) @@ -129,7 +129,7 @@ CacheMemory::findTagInSetIgnorePermissions(int64_t cacheSet, { assert(tag == makeLineAddress(tag)); // search the set for the tags - m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag); + auto it = m_tag_index.find(tag); if (it != m_tag_index.end()) return it->second; return -1; // Not found diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh index 7ce674e61..72805b32b 100644 --- a/src/mem/ruby/structures/CacheMemory.hh +++ b/src/mem/ruby/structures/CacheMemory.hh @@ -31,9 +31,9 @@ #define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ #include <string> +#include <unordered_map> #include <vector> -#include "base/hashmap.hh" #include "base/statistics.hh" #include "mem/protocol/CacheRequestType.hh" #include "mem/protocol/CacheResourceType.hh" @@ -168,7 +168,7 @@ class CacheMemory : public SimObject // The first index is the # of cache lines. // The second index is the the amount associativity. - m5::hash_map<Addr, int> m_tag_index; + std::unordered_map<Addr, int> m_tag_index; std::vector<std::vector<AbstractCacheEntry*> > m_cache; AbstractReplacementPolicy *m_replacementPolicy_ptr; diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh b/src/mem/ruby/structures/PerfectCacheMemory.hh index 2b8b87628..61d5e1244 100644 --- a/src/mem/ruby/structures/PerfectCacheMemory.hh +++ b/src/mem/ruby/structures/PerfectCacheMemory.hh @@ -29,7 +29,8 @@ #ifndef __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ #define __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ -#include "base/hashmap.hh" +#include <unordered_map> + #include "mem/protocol/AccessPermission.hh" #include "mem/ruby/common/Address.hh" @@ -87,7 +88,7 @@ class PerfectCacheMemory PerfectCacheMemory& operator=(const PerfectCacheMemory& obj); // Data Members (m_prefix) - m5::hash_map<Addr, PerfectCacheLineState<ENTRY> > m_map; + std::unordered_map<Addr, PerfectCacheLineState<ENTRY> > m_map; }; template<class ENTRY> diff --git a/src/mem/ruby/structures/PersistentTable.hh b/src/mem/ruby/structures/PersistentTable.hh index a4604fce8..e5296d1e8 100644 --- a/src/mem/ruby/structures/PersistentTable.hh +++ b/src/mem/ruby/structures/PersistentTable.hh @@ -30,8 +30,8 @@ #define __MEM_RUBY_STRUCTURES_PERSISTENTTABLE_HH__ #include <iostream> +#include <unordered_map> -#include "base/hashmap.hh" #include "mem/protocol/AccessType.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/MachineID.hh" @@ -77,7 +77,7 @@ class PersistentTable PersistentTable& operator=(const PersistentTable& obj); // Data Members (m_prefix) - typedef m5::hash_map<Addr, PersistentTableEntry> AddressMap; + typedef std::unordered_map<Addr, PersistentTableEntry> AddressMap; AddressMap m_map; }; diff --git a/src/mem/ruby/structures/RubyMemoryControl.hh b/src/mem/ruby/structures/RubyMemoryControl.hh index f5f31458b..75fe71dfb 100644 --- a/src/mem/ruby/structures/RubyMemoryControl.hh +++ b/src/mem/ruby/structures/RubyMemoryControl.hh @@ -60,7 +60,7 @@ class RubyMemoryControl : public AbstractMemory, public Consumer virtual BaseSlavePort& getSlavePort(const std::string& if_name, PortID idx = InvalidPortID); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; void wakeup(); void setDescription(const std::string& name) { m_description = name; }; diff --git a/src/mem/ruby/structures/TBETable.hh b/src/mem/ruby/structures/TBETable.hh index 4a24a5b13..a39c5af2e 100644 --- a/src/mem/ruby/structures/TBETable.hh +++ b/src/mem/ruby/structures/TBETable.hh @@ -30,8 +30,8 @@ #define __MEM_RUBY_STRUCTURES_TBETABLE_HH__ #include <iostream> +#include <unordered_map> -#include "base/hashmap.hh" #include "mem/ruby/common/Address.hh" template<class ENTRY> @@ -63,7 +63,7 @@ class TBETable TBETable& operator=(const TBETable& obj); // Data Members (m_prefix) - m5::hash_map<Addr, ENTRY> m_map; + std::unordered_map<Addr, ENTRY> m_map; private: int m_number_of_TBEs; |