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-rw-r--r--src/mem/ruby/system/DMASequencer.cc5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 3c895e627..2b65d675a 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -89,8 +89,9 @@ DMASequencer::MemSlavePort::recvTimingReq(PacketPtr pkt)
pkt->getAddr(), id);
DMASequencer *seq = static_cast<DMASequencer *>(&owner);
- if (pkt->memInhibitAsserted())
- panic("DMASequencer should never see an inhibited request\n");
+ if (pkt->cacheResponding())
+ panic("DMASequencer should never see a request with the "
+ "cacheResponding flag set\n");
assert(isPhysMemAddress(pkt->getAddr()));
assert(getOffset(pkt->getAddr()) + pkt->getSize() <=