1 files changed, 2 insertions, 74 deletions

diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index 34f9be34c..9cf187c83 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -32,18 +32,11 @@
 #include <memory>
 #include <ostream>
 
-#include "mem/mem_object.hh"
 #include "mem/protocol/DMASequencerRequestType.hh"
-#include "mem/protocol/RequestStatus.hh"
 #include "mem/ruby/common/DataBlock.hh"
-#include "mem/ruby/network/MessageBuffer.hh"
-#include "mem/ruby/system/RubySystem.hh"
-#include "mem/simple_mem.hh"
-#include "mem/tport.hh"
+#include "mem/ruby/system/RubyPort.hh"
 #include "params/DMASequencer.hh"
 
-class AbstractController;
-
 struct DMARequest
 {
     uint64_t start_paddr;
@@ -55,47 +48,12 @@ struct DMARequest
     PacketPtr pkt;
 };
 
-class DMASequencer : public MemObject
+class DMASequencer : public RubyPort
 {
   public:
     typedef DMASequencerParams Params;
     DMASequencer(const Params *);
     void init() override;
-    RubySystem *m_ruby_system;
-
-  public:
-    class MemSlavePort : public QueuedSlavePort
-    {
-      private:
-        RespPacketQueue queue;
-        RubySystem* m_ruby_system;
-        bool access_backing_store;
-
-      public:
-        MemSlavePort(const std::string &_name, DMASequencer *_port,
-                     PortID id, RubySystem *_ruby_system,
-                     bool _access_backing_store);
-        void hitCallback(PacketPtr pkt);
-        void evictionCallback(Addr address);
-
-      protected:
-        bool recvTimingReq(PacketPtr pkt);
-
-        Tick recvAtomic(PacketPtr pkt)
-        { panic("DMASequencer::MemSlavePort::recvAtomic() not implemented!\n"); }
-
-        void recvFunctional(PacketPtr pkt)
-        { panic("DMASequencer::MemSlavePort::recvFunctional() not implemented!\n"); }
-
-        AddrRangeList getAddrRanges() const
-        { AddrRangeList ranges; return ranges; }
-
-      private:
-        bool isPhysMemAddress(Addr addr) const;
-    };
-
-    BaseSlavePort &getSlavePort(const std::string &if_name,
-                                PortID idx = InvalidPortID) override;
 
     /* external interface */
     RequestStatus makeRequest(PacketPtr pkt);
@@ -104,12 +62,6 @@ class DMASequencer : public MemObject
     bool isDeadlockEventScheduled() const { return false; }
     void descheduleDeadlockEvent() {}
 
-    // Called by the controller to give the sequencer a pointer.
-    // A pointer to the controller is needed for atomic support.
-    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
-    uint32_t getId() { return m_version; }
-    DrainState drain() override;
-
     /* SLICC callback */
     void dataCallback(const DataBlock & dblk);
     void ackCallback();
@@ -118,31 +70,7 @@ class DMASequencer : public MemObject
 
   private:
     void issueNext();
-    void ruby_hit_callback(PacketPtr pkt);
-    void testDrainComplete();
-
-    /**
-     * Called by the PIO port when receiving a timing response.
-     *
-     * @param pkt Response packet
-     * @param master_port_id Port id of the PIO port
-     *
-     * @return Whether successfully sent
-     */
-    bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
-    unsigned int getChildDrainCount();
-
-  private:
-    uint32_t m_version;
-    AbstractController* m_controller;
-    MessageBuffer* m_mandatory_q_ptr;
-    bool m_usingRubyTester;
-
-    MemSlavePort slave_port;
-
-    System* system;
 
-    bool retry;
     bool m_is_busy;
     uint64_t m_data_block_mask;
     DMARequest active_request;