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-rw-r--r--src/mem/ruby/system/RubyPort.cc15
1 files changed, 13 insertions, 2 deletions
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index ab3e6e3b7..2ef65a13a 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -68,13 +68,24 @@ RubyPort::init()
Port *
RubyPort::getPort(const std::string &if_name, int idx)
{
- if (if_name == "port") {
- M5Port* cpuPort = new M5Port(csprintf("%s-port%d", name(), idx),
+ // used by the CPUs to connect the caches to the interconnect, and
+ // for the x86 case also the interrupt master
+ if (if_name == "slave") {
+ M5Port* cpuPort = new M5Port(csprintf("%s-slave%d", name(), idx),
this, ruby_system, access_phys_mem);
cpu_ports.push_back(cpuPort);
return cpuPort;
}
+ // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
+ // port
+ if (if_name == "master") {
+ PioPort* masterPort = new PioPort(csprintf("%s-master%d", name(), idx),
+ this);
+
+ return masterPort;
+ }
+
if (if_name == "pio_port") {
// ensure there is only one pio port
assert(pio_port == NULL);