diff options
Diffstat (limited to 'src/mem/ruby/system/Sequencer.cc')
-rw-r--r-- | src/mem/ruby/system/Sequencer.cc | 42 |
1 files changed, 24 insertions, 18 deletions
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 740db7d8d..305758798 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -317,27 +317,28 @@ Sequencer::removeRequest(SequencerRequest* srequest) void Sequencer::invalidateSC(Addr address) { - AbstractCacheEntry *e = m_dataCache_ptr->lookup(address); - // The controller has lost the coherence permissions, hence the lock - // on the cache line maintained by the cache should be cleared. - if (e && e->isLocked(m_version)) { - e->clearLocked(); + RequestTable::iterator i = m_writeRequestTable.find(address); + if (i != m_writeRequestTable.end()) { + SequencerRequest* request = i->second; + // The controller has lost the coherence permissions, hence the lock + // on the cache line maintained by the cache should be cleared. + if (request->m_type == RubyRequestType_Store_Conditional) { + m_dataCache_ptr->clearLocked(address); + } } } bool Sequencer::handleLlsc(Addr address, SequencerRequest* request) { - AbstractCacheEntry *e = m_dataCache_ptr->lookup(address); - if (!e) - return true; - + // // The success flag indicates whether the LLSC operation was successful. // LL ops will always succeed, but SC may fail if the cache line is no // longer locked. + // bool success = true; if (request->m_type == RubyRequestType_Store_Conditional) { - if (!e->isLocked(m_version)) { + if (!m_dataCache_ptr->isLocked(address, m_version)) { // // For failed SC requests, indicate the failure to the cpu by // setting the extra data to zero. @@ -354,18 +355,19 @@ Sequencer::handleLlsc(Addr address, SequencerRequest* request) // // Independent of success, all SC operations must clear the lock // - e->clearLocked(); + m_dataCache_ptr->clearLocked(address); } else if (request->m_type == RubyRequestType_Load_Linked) { // // Note: To fully follow Alpha LLSC semantics, should the LL clear any // previously locked cache lines? // - e->setLocked(m_version); - } else if (e->isLocked(m_version)) { + m_dataCache_ptr->setLocked(address, m_version); + } else if ((m_dataCache_ptr->isTagPresent(address)) && + (m_dataCache_ptr->isLocked(address, m_version))) { // // Normal writes should clear the locked address // - e->clearLocked(); + m_dataCache_ptr->clearLocked(address); } return success; } @@ -496,15 +498,19 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data, const Cycles forwardRequestTime, const Cycles firstResponseTime) { - warn_once("Replacement policy updates recently became the responsibility " - "of SLICC state machines. Make sure to setMRU() near callbacks " - "in .sm files!"); - PacketPtr pkt = srequest->pkt; Addr request_address(pkt->getAddr()); + Addr request_line_address = makeLineAddress(pkt->getAddr()); RubyRequestType type = srequest->m_type; Cycles issued_time = srequest->issue_time; + // Set this cache entry to the most recently used + if (type == RubyRequestType_IFETCH) { + m_instCache_ptr->setMRU(request_line_address); + } else { + m_dataCache_ptr->setMRU(request_line_address); + } + assert(curCycle() >= issued_time); Cycles total_latency = curCycle() - issued_time; |