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-rw-r--r--src/mem/ruby/system/Sequencer.hh7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 5dd674655..cd936a528 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -45,6 +45,7 @@
#include "GenericMachineType.hh"
#include "PrefetchBit.hh"
#include "Map.hh"
+#include "packet.hh"
class DataBlock;
class AbstractChip;
@@ -108,10 +109,12 @@ public:
void printDebug();
// called by Tester or Simics
- void makeRequest(const CacheMsg& request);
+ void makeRequest(const Packet* pkt, void* data);
+ void makeRequest(const CacheMsg& request); // depricate this function
bool doRequest(const CacheMsg& request);
void issueRequest(const CacheMsg& request);
- bool isReady(const CacheMsg& request) const;
+ bool isReady(const Packet* pkt) const;
+ bool isReady(const CacheMsg& request) const; // depricate this function
bool empty() const;
void resetRequestTime(const Address& addr, int thread);
Address getLogicalAddressOfRequest(Address address, int thread);