diff options
Diffstat (limited to 'src/mem/ruby/system/Sequencer.hh')
| -rw-r--r-- | src/mem/ruby/system/Sequencer.hh | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 505b3f3bc..c4ed6f21e 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -68,7 +68,7 @@ class Sequencer : public RubyPort void collateStats(); void regStats(); - void writeCallback(const Address& address, + void writeCallback(Addr address, DataBlock& data, const bool externalHit = false, const MachineType mach = MachineType_NUM, @@ -76,7 +76,7 @@ class Sequencer : public RubyPort const Cycles forwardRequestTime = Cycles(0), const Cycles firstResponseTime = Cycles(0)); - void readCallback(const Address& address, + void readCallback(Addr address, DataBlock& data, const bool externalHit = false, const MachineType mach = MachineType_NUM, @@ -95,12 +95,12 @@ class Sequencer : public RubyPort { deschedule(deadlockCheckEvent); } void print(std::ostream& out) const; - void checkCoherence(const Address& address); + void checkCoherence(Addr address); void markRemoved(); void removeRequest(SequencerRequest* request); - void evictionCallback(const Address& address); - void invalidateSC(const Address& address); + void evictionCallback(Addr address); + void invalidateSC(Addr address); void recordRequestType(SequencerRequestType requestType); Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; } @@ -167,7 +167,7 @@ class Sequencer : public RubyPort Cycles completionTime); RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type); - bool handleLlsc(const Address& address, SequencerRequest* request); + bool handleLlsc(Addr address, SequencerRequest* request); // Private copy constructor and assignment operator Sequencer(const Sequencer& obj); @@ -187,7 +187,7 @@ class Sequencer : public RubyPort Cycles m_data_cache_hit_latency; Cycles m_inst_cache_hit_latency; - typedef m5::hash_map<Address, SequencerRequest*> RequestTable; + typedef m5::hash_map<Addr, SequencerRequest*> RequestTable; RequestTable m_writeRequestTable; RequestTable m_readRequestTable; // Global outstanding request count, across all request tables |