1 files changed, 15 insertions, 19 deletions

diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 33fd53064..71ffa99bf 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -30,6 +30,7 @@
 #define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
 
 #include <iostream>
+#include <list>
 #include <unordered_map>
 
 #include "mem/ruby/common/Address.hh"
@@ -44,11 +45,12 @@ struct SequencerRequest
 {
     PacketPtr pkt;
     RubyRequestType m_type;
+    RubyRequestType m_second_type;
     Cycles issue_time;
-
     SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type,
-                     Cycles _issue_time)
-        : pkt(_pkt), m_type(_m_type), issue_time(_issue_time)
+                     RubyRequestType _m_second_type, Cycles _issue_time)
+                : pkt(_pkt), m_type(_m_type), m_second_type(_m_second_type),
+                  issue_time(_issue_time)
     {}
 };
 
@@ -151,21 +153,21 @@ class Sequencer : public RubyPort
   private:
     void issueRequest(PacketPtr pkt, RubyRequestType type);
 
-    void hitCallback(SequencerRequest* request, DataBlock& data,
+    void hitCallback(SequencerRequest* srequest, DataBlock& data,
                      bool llscSuccess,
                      const MachineType mach, const bool externalHit,
                      const Cycles initialRequestTime,
                      const Cycles forwardRequestTime,
                      const Cycles firstResponseTime);
 
-    void recordMissLatency(const Cycles t, const RubyRequestType type,
+    void recordMissLatency(SequencerRequest* srequest, bool llscSuccess,
                            const MachineType respondingMach,
-                           bool isExternalHit, Cycles issuedTime,
-                           Cycles initialRequestTime,
-                           Cycles forwardRequestTime, Cycles firstResponseTime,
-                           Cycles completionTime);
+                           bool isExternalHit, Cycles initialRequestTime,
+                           Cycles forwardRequestTime,
+                           Cycles firstResponseTime);
 
-    RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type);
+    RequestStatus insertRequest(PacketPtr pkt, RubyRequestType primary_type,
+                                RubyRequestType secondary_type);
     bool handleLlsc(Addr address, SequencerRequest* request);
 
     // Private copy constructor and assignment operator
@@ -186,19 +188,13 @@ class Sequencer : public RubyPort
     Cycles m_data_cache_hit_latency;
     Cycles m_inst_cache_hit_latency;
 
-    typedef std::unordered_map<Addr, SequencerRequest*> RequestTable;
-    RequestTable m_writeRequestTable;
-    RequestTable m_readRequestTable;
+    // RequestTable contains both read and write requests, handles aliasing
+    std::unordered_map<Addr, std::list<SequencerRequest>> m_RequestTable;
+
     // Global outstanding request count, across all request tables
     int m_outstanding_count;
     bool m_deadlock_check_scheduled;
 
-    //! Counters for recording aliasing information.
-    Stats::Scalar m_store_waiting_on_load;
-    Stats::Scalar m_store_waiting_on_store;
-    Stats::Scalar m_load_waiting_on_store;
-    Stats::Scalar m_load_waiting_on_load;
-
     int m_coreId;
 
     bool m_runningGarnetStandalone;