summaryrefslogtreecommitdiff
path: root/src/mem/ruby/system/Sequencer.py
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem/ruby/system/Sequencer.py')
-rw-r--r--src/mem/ruby/system/Sequencer.py4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index deef6e714..9b243a8b9 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -34,6 +34,7 @@ from MemObject import MemObject
class RubyPort(MemObject):
type = 'RubyPort'
abstract = True
+ cxx_header = "mem/ruby/system/RubyPort.hh"
slave = VectorSlavePort("CPU slave port")
master = VectorMasterPort("CPU master port")
version = Param.Int(0, "")
@@ -50,10 +51,12 @@ class RubyPort(MemObject):
class RubyPortProxy(RubyPort):
type = 'RubyPortProxy'
+ cxx_header = "mem/ruby/system/RubyPortProxy.hh"
class RubySequencer(RubyPort):
type = 'RubySequencer'
cxx_class = 'Sequencer'
+ cxx_header = "mem/ruby/system/Sequencer.hh"
icache = Param.RubyCache("")
dcache = Param.RubyCache("")
max_outstanding_requests = Param.Int(16,
@@ -63,3 +66,4 @@ class RubySequencer(RubyPort):
class DMASequencer(RubyPort):
type = 'DMASequencer'
+ cxx_header = "mem/ruby/system/DMASequencer.hh"