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-rw-r--r--src/mem/ruby/system/Sequencer.py4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index 9b243a8b9..68d02f53c 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -41,7 +41,7 @@ class RubyPort(MemObject):
pio_port = MasterPort("Ruby_pio_port")
using_ruby_tester = Param.Bool(False, "")
using_network_tester = Param.Bool(False, "")
- access_phys_mem = Param.Bool(True,
+ access_phys_mem = Param.Bool(False,
"should the rubyport atomically update phys_mem")
ruby_system = Param.RubySystem("")
system = Param.System(Parent.any, "system object")
@@ -52,6 +52,7 @@ class RubyPort(MemObject):
class RubyPortProxy(RubyPort):
type = 'RubyPortProxy'
cxx_header = "mem/ruby/system/RubyPortProxy.hh"
+ access_phys_mem = True
class RubySequencer(RubyPort):
type = 'RubySequencer'
@@ -67,3 +68,4 @@ class RubySequencer(RubyPort):
class DMASequencer(RubyPort):
type = 'DMASequencer'
cxx_header = "mem/ruby/system/DMASequencer.hh"
+ access_phys_mem = True