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-rw-r--r--src/mem/ruby/system/Sequencer.cc34
-rw-r--r--src/mem/ruby/system/Sequencer.hh44
-rw-r--r--src/mem/ruby/system/TBETable.hh3
-rw-r--r--src/mem/ruby/system/TimerTable.cc2
-rw-r--r--src/mem/ruby/system/TimerTable.hh2
5 files changed, 41 insertions, 44 deletions
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 3481369bb..94ad42d9d 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -359,19 +359,19 @@ Sequencer::writeCallback(const Address& address, DataBlock& data)
void
Sequencer::writeCallback(const Address& address,
- GenericMachineType mach,
+ GenericMachineType mach,
DataBlock& data)
{
- writeCallback(address, mach, data, 0, 0, 0);
+ writeCallback(address, mach, data, Cycles(0), Cycles(0), Cycles(0));
}
void
Sequencer::writeCallback(const Address& address,
- GenericMachineType mach,
+ GenericMachineType mach,
DataBlock& data,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime)
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime)
{
assert(address == line_address(address));
assert(m_writeRequestTable.count(line_address(address)));
@@ -410,7 +410,7 @@ Sequencer::writeCallback(const Address& address,
m_controller->unblock(address);
}
- hitCallback(request, mach, data, success,
+ hitCallback(request, mach, data, success,
initialRequestTime, forwardRequestTime, firstResponseTime);
}
@@ -425,16 +425,16 @@ Sequencer::readCallback(const Address& address,
GenericMachineType mach,
DataBlock& data)
{
- readCallback(address, mach, data, 0, 0, 0);
+ readCallback(address, mach, data, Cycles(0), Cycles(0), Cycles(0));
}
void
Sequencer::readCallback(const Address& address,
GenericMachineType mach,
DataBlock& data,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime)
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime)
{
assert(address == line_address(address));
assert(m_readRequestTable.count(line_address(address)));
@@ -449,7 +449,7 @@ Sequencer::readCallback(const Address& address,
assert((request->m_type == RubyRequestType_LD) ||
(request->m_type == RubyRequestType_IFETCH));
- hitCallback(request, mach, data, true,
+ hitCallback(request, mach, data, true,
initialRequestTime, forwardRequestTime, firstResponseTime);
}
@@ -458,16 +458,16 @@ Sequencer::hitCallback(SequencerRequest* srequest,
GenericMachineType mach,
DataBlock& data,
bool success,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime)
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime)
{
PacketPtr pkt = srequest->pkt;
Address request_address(pkt->getAddr());
Address request_line_address(pkt->getAddr());
request_line_address.makeLineAddress();
RubyRequestType type = srequest->m_type;
- Time issued_time = srequest->issue_time;
+ Cycles issued_time = srequest->issue_time;
// Set this cache entry to the most recently used
if (type == RubyRequestType_IFETCH) {
@@ -477,7 +477,7 @@ Sequencer::hitCallback(SequencerRequest* srequest,
}
assert(curCycle() >= issued_time);
- Time miss_latency = curCycle() - issued_time;
+ Cycles miss_latency = curCycle() - issued_time;
// Profile the miss latency for all non-zero demand misses
if (miss_latency != 0) {
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 3fccd2566..b3ec4d10a 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -70,29 +70,29 @@ class Sequencer : public RubyPort
void writeCallback(const Address& address, DataBlock& data);
- void writeCallback(const Address& address,
- GenericMachineType mach,
+ void writeCallback(const Address& address,
+ GenericMachineType mach,
DataBlock& data);
- void writeCallback(const Address& address,
- GenericMachineType mach,
+ void writeCallback(const Address& address,
+ GenericMachineType mach,
DataBlock& data,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime);
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime);
void readCallback(const Address& address, DataBlock& data);
- void readCallback(const Address& address,
- GenericMachineType mach,
+ void readCallback(const Address& address,
+ GenericMachineType mach,
DataBlock& data);
- void readCallback(const Address& address,
- GenericMachineType mach,
+ void readCallback(const Address& address,
+ GenericMachineType mach,
DataBlock& data,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime);
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime);
RequestStatus makeRequest(PacketPtr pkt);
bool empty() const;
@@ -122,13 +122,13 @@ class Sequencer : public RubyPort
private:
void issueRequest(PacketPtr pkt, RubyRequestType type);
- void hitCallback(SequencerRequest* request,
+ void hitCallback(SequencerRequest* request,
GenericMachineType mach,
DataBlock& data,
bool success,
- Time initialRequestTime,
- Time forwardRequestTime,
- Time firstResponseTime);
+ Cycles initialRequestTime,
+ Cycles forwardRequestTime,
+ Cycles firstResponseTime);
RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type);
@@ -152,10 +152,10 @@ class Sequencer : public RubyPort
int m_outstanding_count;
bool m_deadlock_check_scheduled;
- int m_store_waiting_on_load_cycles;
- int m_store_waiting_on_store_cycles;
- int m_load_waiting_on_store_cycles;
- int m_load_waiting_on_load_cycles;
+ uint32_t m_store_waiting_on_load_cycles;
+ uint32_t m_store_waiting_on_store_cycles;
+ uint32_t m_load_waiting_on_store_cycles;
+ uint32_t m_load_waiting_on_load_cycles;
bool m_usingNetworkTester;
diff --git a/src/mem/ruby/system/TBETable.hh b/src/mem/ruby/system/TBETable.hh
index fa4493757..018da6cbb 100644
--- a/src/mem/ruby/system/TBETable.hh
+++ b/src/mem/ruby/system/TBETable.hh
@@ -33,9 +33,6 @@
#include "base/hashmap.hh"
#include "mem/ruby/common/Address.hh"
-#include "mem/ruby/common/Global.hh"
-#include "mem/ruby/profiler/Profiler.hh"
-#include "mem/ruby/system/System.hh"
template<class ENTRY>
class TBETable
diff --git a/src/mem/ruby/system/TimerTable.cc b/src/mem/ruby/system/TimerTable.cc
index d87f11662..d29491611 100644
--- a/src/mem/ruby/system/TimerTable.cc
+++ b/src/mem/ruby/system/TimerTable.cc
@@ -31,13 +31,13 @@
#include "mem/ruby/system/TimerTable.hh"
TimerTable::TimerTable()
+ : m_next_time(0)
{
m_consumer_ptr = NULL;
m_clockobj_ptr = NULL;
m_next_valid = false;
m_next_address = Address(0);
- m_next_time = 0;
}
bool
diff --git a/src/mem/ruby/system/TimerTable.hh b/src/mem/ruby/system/TimerTable.hh
index 95af2eaa7..b271d3e37 100644
--- a/src/mem/ruby/system/TimerTable.hh
+++ b/src/mem/ruby/system/TimerTable.hh
@@ -85,7 +85,7 @@ class TimerTable
typedef std::map<Address, Cycles> AddressMap;
AddressMap m_map;
mutable bool m_next_valid;
- mutable Time m_next_time; // Only valid if m_next_valid is true
+ mutable Cycles m_next_time; // Only valid if m_next_valid is true
mutable Address m_next_address; // Only valid if m_next_valid is true
//! Object used for querying time.
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 04:20:41 +0000