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-rw-r--r--src/mem/ruby/system/DMASequencer.cc1
-rw-r--r--src/mem/ruby/system/TBETable.hh1
2 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 58ec7bb45..d29dba602 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -51,6 +51,7 @@ int64_t DMASequencer::makeRequest(const RubyRequest & request)
case RubyRequestType_Locked_Write:
case RubyRequestType_RMW_Read:
case RubyRequestType_RMW_Write:
+ case RubyRequestType_NUM:
assert(0);
}
diff --git a/src/mem/ruby/system/TBETable.hh b/src/mem/ruby/system/TBETable.hh
index 7d2daa55a..2b00f7a06 100644
--- a/src/mem/ruby/system/TBETable.hh
+++ b/src/mem/ruby/system/TBETable.hh
@@ -128,7 +128,6 @@ void TBETable<ENTRY>::allocate(const Address& address)
{
assert(isPresent(address) == false);
assert(m_map.size() < m_number_of_TBEs);
- g_system_ptr->getProfiler()->L2tbeUsageSample(m_map.size());
m_map.add(address, ENTRY());
}