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-rw-r--r--src/mem/ruby/system/DMASequencer.cc36
-rw-r--r--src/mem/ruby/system/MemoryControl.cc6
-rw-r--r--src/mem/ruby/system/Sequencer.cc6
3 files changed, 24 insertions, 24 deletions
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 5d9037358..a7f3a8aec 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -82,22 +82,22 @@ DMASequencer::makeRequest(const RubyRequest &request)
active_request.bytes_issued = 0;
active_request.pkt = request.pkt;
- SequencerMsg msg;
- msg.getPhysicalAddress() = Address(paddr);
- msg.getLineAddress() = line_address(msg.getPhysicalAddress());
- msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
+ SequencerMsg *msg = new SequencerMsg;
+ msg->getPhysicalAddress() = Address(paddr);
+ msg->getLineAddress() = line_address(msg->getPhysicalAddress());
+ msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
int offset = paddr & m_data_block_mask;
- msg.getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
+ msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
len : RubySystem::getBlockSizeBytes() - offset;
if (write) {
- msg.getDataBlk().setData(data, offset, msg.getLen());
+ msg->getDataBlk().setData(data, offset, msg->getLen());
}
assert(m_mandatory_q_ptr != NULL);
m_mandatory_q_ptr->enqueue(msg);
- active_request.bytes_issued += msg.getLen();
+ active_request.bytes_issued += msg->getLen();
return RequestStatus_Issued;
}
@@ -113,34 +113,34 @@ DMASequencer::issueNext()
return;
}
- SequencerMsg msg;
- msg.getPhysicalAddress() = Address(active_request.start_paddr +
+ SequencerMsg *msg = new SequencerMsg;
+ msg->getPhysicalAddress() = Address(active_request.start_paddr +
active_request.bytes_completed);
- assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
- msg.getLineAddress() = line_address(msg.getPhysicalAddress());
+ assert((msg->getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
+ msg->getLineAddress() = line_address(msg->getPhysicalAddress());
- msg.getType() = (active_request.write ? SequencerRequestType_ST :
+ msg->getType() = (active_request.write ? SequencerRequestType_ST :
SequencerRequestType_LD);
- msg.getLen() =
+ msg->getLen() =
(active_request.len -
active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
active_request.len - active_request.bytes_completed :
RubySystem::getBlockSizeBytes());
if (active_request.write) {
- msg.getDataBlk().
+ msg->getDataBlk().
setData(&active_request.data[active_request.bytes_completed],
- 0, msg.getLen());
- msg.getType() = SequencerRequestType_ST;
+ 0, msg->getLen());
+ msg->getType() = SequencerRequestType_ST;
} else {
- msg.getType() = SequencerRequestType_LD;
+ msg->getType() = SequencerRequestType_LD;
}
assert(m_mandatory_q_ptr != NULL);
m_mandatory_q_ptr->enqueue(msg);
- active_request.bytes_issued += msg.getLen();
+ active_request.bytes_issued += msg->getLen();
}
void
diff --git a/src/mem/ruby/system/MemoryControl.cc b/src/mem/ruby/system/MemoryControl.cc
index 3644a3e59..5c455049e 100644
--- a/src/mem/ruby/system/MemoryControl.cc
+++ b/src/mem/ruby/system/MemoryControl.cc
@@ -239,7 +239,7 @@ MemoryControl::enqueue(const MsgPtr& message, int latency)
{
Time current_time = g_eventQueue_ptr->getTime();
Time arrival_time = current_time + latency;
- const MemoryMsg* memMess = dynamic_cast<const MemoryMsg*>(message.ref());
+ const MemoryMsg* memMess = safe_cast<const MemoryMsg*>(message.get());
physical_address_t addr = memMess->getAddress().getAddress();
MemoryRequestType type = memMess->getType();
bool is_mem_read = (type == MemoryRequestType_MEMORY_READ);
@@ -285,7 +285,7 @@ const Message*
MemoryControl::peek()
{
MemoryNode node = peekNode();
- Message* msg_ptr = node.m_msgptr.ref();
+ Message* msg_ptr = node.m_msgptr.get();
assert(msg_ptr != NULL);
return msg_ptr;
}
@@ -536,7 +536,7 @@ MemoryControl::issueRequest(int bank)
req.m_msg_counter, req.m_addr, req.m_is_mem_read? 'R':'W',
current_time, bank);
}
- if (req.m_msgptr.ref() != NULL) { // don't enqueue L3 writebacks
+ if (req.m_msgptr) { // don't enqueue L3 writebacks
enqueueToDirectory(req, m_mem_ctl_latency + m_mem_fixed_delay);
}
m_oldRequest[bank] = 0;
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index dd8cec967..641c8fcb9 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -536,9 +536,9 @@ Sequencer::issueRequest(const RubyRequest& request)
Address line_addr(request.paddr);
line_addr.makeLineAddress();
- CacheMsg msg(line_addr, Address(request.paddr), ctype,
- Address(request.pc), amtype, request.len, PrefetchBit_No,
- request.proc_id);
+ CacheMsg *msg = new CacheMsg(line_addr, Address(request.paddr), ctype,
+ Address(request.pc), amtype, request.len, PrefetchBit_No,
+ request.proc_id);
if (Debug::getProtocolTrace()) {
g_system_ptr->getProfiler()->