diff options
Diffstat (limited to 'src/mem/ruby/system')
| -rw-r--r-- | src/mem/ruby/system/Sequencer.cc | 17 | ||||
| -rw-r--r-- | src/mem/ruby/system/Sequencer.hh | 7 | ||||
| -rw-r--r-- | src/mem/ruby/system/Sequencer.py | 6 |
3 files changed, 26 insertions, 4 deletions
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 01b868017..36bd9cd62 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -58,6 +58,8 @@ Sequencer::Sequencer(const Params *p) m_instCache_ptr = p->icache; m_dataCache_ptr = p->dcache; + m_data_cache_hit_latency = p->dcache_hit_latency; + m_inst_cache_hit_latency = p->icache_hit_latency; m_max_outstanding_requests = p->max_outstanding_requests; m_deadlock_threshold = p->deadlock_threshold; @@ -65,6 +67,8 @@ Sequencer::Sequencer(const Params *p) assert(m_deadlock_threshold > 0); assert(m_instCache_ptr != NULL); assert(m_dataCache_ptr != NULL); + assert(m_data_cache_hit_latency > 0); + assert(m_inst_cache_hit_latency > 0); m_usingNetworkTester = p->using_network_tester; } @@ -691,12 +695,17 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) msg->getPhysicalAddress(), RubyRequestType_to_string(secondary_type)); - Cycles latency(0); // initialzed to an null value - + // The Sequencer currently assesses instruction and data cache hit latency + // for the top-level caches at the beginning of a memory access. + // TODO: Eventually, this latency should be moved to represent the actual + // cache access latency portion of the memory access. This will require + // changing cache controller protocol files to assess the latency on the + // access response path. + Cycles latency(0); // Initialize to zero to catch misconfigured latency if (secondary_type == RubyRequestType_IFETCH) - latency = m_instCache_ptr->getLatency(); + latency = m_inst_cache_hit_latency; else - latency = m_dataCache_ptr->getLatency(); + latency = m_data_cache_hit_latency; // Send the message to the cache controller assert(latency > 0); diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index d5cd17f5f..505b3f3bc 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -180,6 +180,13 @@ class Sequencer : public RubyPort CacheMemory* m_dataCache_ptr; CacheMemory* m_instCache_ptr; + // The cache access latency for top-level caches (L0/L1). These are + // currently assessed at the beginning of each memory access through the + // sequencer. + // TODO: Migrate these latencies into top-level cache controllers. + Cycles m_data_cache_hit_latency; + Cycles m_inst_cache_hit_latency; + typedef m5::hash_map<Address, SequencerRequest*> RequestTable; RequestTable m_writeRequestTable; RequestTable m_readRequestTable; diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index e545000cf..7494986e9 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -61,6 +61,12 @@ class RubySequencer(RubyPort): icache = Param.RubyCache("") dcache = Param.RubyCache("") + # Cache latencies currently assessed at the beginning of each access + # NOTE: Setting these values to a value greater than one will result in + # O3 CPU pipeline bubbles and negatively impact performance + # TODO: Latencies should be migrated into each top-level cache controller + icache_hit_latency = Param.Cycles(1, "Inst cache hit latency") + dcache_hit_latency = Param.Cycles(1, "Data cache hit latency") max_outstanding_requests = Param.Int(16, "max requests (incl. prefetches) outstanding") deadlock_threshold = Param.Cycles(500000, |