diff options
Diffstat (limited to 'src/mem/ruby/system')
| -rw-r--r-- | src/mem/ruby/system/RubySystem.cc | 4 | ||||
| -rw-r--r-- | src/mem/ruby/system/Sequencer.cc | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/mem/ruby/system/RubySystem.cc b/src/mem/ruby/system/RubySystem.cc index 454775178..3ad3911cb 100644 --- a/src/mem/ruby/system/RubySystem.cc +++ b/src/mem/ruby/system/RubySystem.cc @@ -404,7 +404,7 @@ RubySystem::functionalRead(PacketPtr pkt) AccessPermission access_perm = AccessPermission_NotPresent; int num_controllers = m_abs_cntrl_vec.size(); - DPRINTF(RubySystem, "Functional Read request for %s\n", address); + DPRINTF(RubySystem, "Functional Read request for %#x\n", address); unsigned int num_ro = 0; unsigned int num_rw = 0; @@ -486,7 +486,7 @@ RubySystem::functionalWrite(PacketPtr pkt) AccessPermission access_perm = AccessPermission_NotPresent; int num_controllers = m_abs_cntrl_vec.size(); - DPRINTF(RubySystem, "Functional Write request for %s\n", addr); + DPRINTF(RubySystem, "Functional Write request for %#x\n", addr); uint32_t M5_VAR_USED num_functional_writes = 0; diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 815e270b6..aa4ac742a 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -443,7 +443,7 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data, DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n", curTick(), m_version, "Seq", llscSuccess ? "Done" : "SC_Failed", "", "", - request_address, total_latency); + printAddress(request_address), total_latency); // update the data unless it is a non-data-carrying flush if (RubySystem::getWarmupEnabled()) { @@ -610,7 +610,7 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n", curTick(), m_version, "Seq", "Begin", "", "", - msg->getPhysicalAddress(), + printAddress(msg->getPhysicalAddress()), RubyRequestType_to_string(secondary_type)); // The Sequencer currently assesses instruction and data cache hit latency |