diff options
Diffstat (limited to 'src/mem/ruby/system')
22 files changed, 0 insertions, 170 deletions
diff --git a/src/mem/ruby/system/AbstractMemOrCache.hh b/src/mem/ruby/system/AbstractMemOrCache.hh index 88f9f4d87..4d1fee69a 100644 --- a/src/mem/ruby/system/AbstractMemOrCache.hh +++ b/src/mem/ruby/system/AbstractMemOrCache.hh @@ -51,7 +51,6 @@ class AbstractMemOrCache virtual bool isReady () = 0; virtual MemoryNode peekNode () = 0; virtual bool areNSlotsAvailable (int n) = 0; - virtual void printConfig (std::ostream& out) = 0; virtual void print (std::ostream& out) const = 0; }; diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc index a8e3523d3..6ba879e90 100644 --- a/src/mem/ruby/system/CacheMemory.cc +++ b/src/mem/ruby/system/CacheMemory.cc @@ -105,31 +105,6 @@ CacheMemory::~CacheMemory() } } -void -CacheMemory::printConfig(ostream& out) -{ - int block_size = RubySystem::getBlockSizeBytes(); - - out << "Cache config: " << m_cache_name << endl; - out << " cache_associativity: " << m_cache_assoc << endl; - out << " num_cache_sets_bits: " << m_cache_num_set_bits << endl; - const int cache_num_sets = 1 << m_cache_num_set_bits; - out << " num_cache_sets: " << cache_num_sets << endl; - out << " cache_set_size_bytes: " << cache_num_sets * block_size << endl; - out << " cache_set_size_Kbytes: " - << double(cache_num_sets * block_size) / (1<<10) << endl; - out << " cache_set_size_Mbytes: " - << double(cache_num_sets * block_size) / (1<<20) << endl; - out << " cache_size_bytes: " - << cache_num_sets * block_size * m_cache_assoc << endl; - out << " cache_size_Kbytes: " - << double(cache_num_sets * block_size * m_cache_assoc) / (1<<10) - << endl; - out << " cache_size_Mbytes: " - << double(cache_num_sets * block_size * m_cache_assoc) / (1<<20) - << endl; -} - // convert a Address to its location in the cache Index CacheMemory::addressToCacheSet(const Address& address) const diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh index ee3c1a7fc..8adc892a7 100644 --- a/src/mem/ruby/system/CacheMemory.hh +++ b/src/mem/ruby/system/CacheMemory.hh @@ -60,8 +60,6 @@ class CacheMemory : public SimObject void init(); // Public Methods - void printConfig(std::ostream& out); - // perform a cache access and see if we hit or not. Return true on a hit. bool tryCacheAccess(const Address& address, RubyRequestType type, DataBlock*& data_ptr); diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc index b1502573b..84450fda4 100644 --- a/src/mem/ruby/system/DMASequencer.cc +++ b/src/mem/ruby/system/DMASequencer.cc @@ -165,11 +165,6 @@ DMASequencer::ackCallback() } void -DMASequencer::printConfig(std::ostream & out) -{ -} - -void DMASequencer::recordRequestType(DMASequencerRequestType requestType) { DPRINTF(RubyStats, "Recorded statistic: %s\n", DMASequencerRequestType_to_string(requestType)); diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh index d1fb2ff49..ce85c20c7 100644 --- a/src/mem/ruby/system/DMASequencer.hh +++ b/src/mem/ruby/system/DMASequencer.hh @@ -64,8 +64,6 @@ class DMASequencer : public RubyPort void dataCallback(const DataBlock & dblk); void ackCallback(); - void printConfig(std::ostream & out); - void recordRequestType(DMASequencerRequestType requestType); private: diff --git a/src/mem/ruby/system/DirectoryMemory.cc b/src/mem/ruby/system/DirectoryMemory.cc index c67babda4..b44f77435 100644 --- a/src/mem/ruby/system/DirectoryMemory.cc +++ b/src/mem/ruby/system/DirectoryMemory.cc @@ -92,34 +92,6 @@ DirectoryMemory::~DirectoryMemory() } } -void -DirectoryMemory::printConfig(ostream& out) const -{ - out << "DirectoryMemory module config: " << m_name << endl - << " version: " << m_version << endl - << " memory_bits: " << m_size_bits << endl - << " memory_size_bytes: " << m_size_bytes << endl - << " memory_size_Kbytes: " << double(m_size_bytes) / (1<<10) << endl - << " memory_size_Mbytes: " << double(m_size_bytes) / (1<<20) << endl - << " memory_size_Gbytes: " << double(m_size_bytes) / (1<<30) << endl; -} - -// Static method -void -DirectoryMemory::printGlobalConfig(ostream & out) -{ - out << "DirectoryMemory Global Config: " << endl; - out << " number of directory memories: " << m_num_directories << endl; - if (m_num_directories > 1) { - out << " number of selection bits: " << m_num_directories_bits << endl - << " selection bits: " << m_numa_high_bit - << "-" << m_numa_high_bit-m_num_directories_bits - << endl; - } - out << " total memory size bytes: " << m_total_size_bytes << endl; - out << " total memory bits: " << floorLog2(m_total_size_bytes) << endl; -} - uint64 DirectoryMemory::mapAddressToDirectoryVersion(PhysAddress address) { diff --git a/src/mem/ruby/system/DirectoryMemory.hh b/src/mem/ruby/system/DirectoryMemory.hh index 61938f7c8..c47a73089 100644 --- a/src/mem/ruby/system/DirectoryMemory.hh +++ b/src/mem/ruby/system/DirectoryMemory.hh @@ -55,8 +55,6 @@ class DirectoryMemory : public SimObject bool isSparseImplementation() { return m_use_map; } uint64 getSize() { return m_size_bytes; } - void printConfig(std::ostream& out) const; - static void printGlobalConfig(std::ostream & out); bool isPresent(PhysAddress address); AbstractEntry* lookup(PhysAddress address); AbstractEntry* allocate(const PhysAddress& address, diff --git a/src/mem/ruby/system/MemoryControl.cc b/src/mem/ruby/system/MemoryControl.cc index 14a34be4a..c5f6ecb83 100644 --- a/src/mem/ruby/system/MemoryControl.cc +++ b/src/mem/ruby/system/MemoryControl.cc @@ -60,5 +60,3 @@ RubyMemoryControlParams::create() { return new RubyMemoryControl(this); } - - diff --git a/src/mem/ruby/system/MemoryControl.hh b/src/mem/ruby/system/MemoryControl.hh index 6a3ca48d9..80a55e9c1 100644 --- a/src/mem/ruby/system/MemoryControl.hh +++ b/src/mem/ruby/system/MemoryControl.hh @@ -76,10 +76,6 @@ class MemoryControl : virtual bool isReady() = 0; virtual bool areNSlotsAvailable(int n) = 0; // infinite queue length - //// Called from L3 cache: - //void writeBack(physical_address_t addr); - - virtual void printConfig(std::ostream& out) = 0; virtual void print(std::ostream& out) const = 0; virtual void clearStats() const = 0; virtual void printStats(std::ostream& out) const = 0; diff --git a/src/mem/ruby/system/PerfectCacheMemory.hh b/src/mem/ruby/system/PerfectCacheMemory.hh index 33419c5c7..b56543c41 100644 --- a/src/mem/ruby/system/PerfectCacheMemory.hh +++ b/src/mem/ruby/system/PerfectCacheMemory.hh @@ -54,8 +54,6 @@ class PerfectCacheMemory public: PerfectCacheMemory(); - static void printConfig(std::ostream& out); - // tests to see if an address is present in the cache bool isTagPresent(const Address& address) const; @@ -107,12 +105,6 @@ PerfectCacheMemory<ENTRY>::PerfectCacheMemory() { } -template<class ENTRY> -inline void -PerfectCacheMemory<ENTRY>::printConfig(std::ostream& out) -{ -} - // tests to see if an address is present in the cache template<class ENTRY> inline bool diff --git a/src/mem/ruby/system/PersistentTable.hh b/src/mem/ruby/system/PersistentTable.hh index a57b3ec76..f634c35d1 100644 --- a/src/mem/ruby/system/PersistentTable.hh +++ b/src/mem/ruby/system/PersistentTable.hh @@ -69,8 +69,6 @@ class PersistentTable int countStarvingForAddress(const Address& addr) const; int countReadStarvingForAddress(const Address& addr) const; - static void printConfig(std::ostream& out) {} - void print(std::ostream& out) const; private: diff --git a/src/mem/ruby/system/RubyMemoryControl.cc b/src/mem/ruby/system/RubyMemoryControl.cc index 4879f4fa6..54585e275 100644 --- a/src/mem/ruby/system/RubyMemoryControl.cc +++ b/src/mem/ruby/system/RubyMemoryControl.cc @@ -362,37 +362,6 @@ RubyMemoryControl::print(ostream& out) const } void -RubyMemoryControl::printConfig(ostream& out) -{ - out << "Memory Control " << name() << ":" << endl; - out << " Ruby cycles per memory cycle: " << m_mem_bus_cycle_multiplier - << endl; - out << " Basic read latency: " << m_mem_ctl_latency << endl; - if (m_mem_fixed_delay) { - out << " Fixed Latency mode: Added cycles = " << m_mem_fixed_delay - << endl; - } else { - out << " Bank busy time: " << m_bank_busy_time << " memory cycles" - << endl; - out << " Memory channel busy time: " << m_basic_bus_busy_time << endl; - out << " Dead cycles between reads to different ranks: " - << m_rank_rank_delay << endl; - out << " Dead cycle between a read and a write: " - << m_read_write_delay << endl; - out << " tFaw (four-activate) window: " << m_tFaw << endl; - } - out << " Banks per rank: " << m_banks_per_rank << endl; - out << " Ranks per DIMM: " << m_ranks_per_dimm << endl; - out << " DIMMs per channel: " << m_dimms_per_channel << endl; - out << " LSB of bank field in address: " << m_bank_bit_0 << endl; - out << " LSB of rank field in address: " << m_rank_bit_0 << endl; - out << " LSB of DIMM field in address: " << m_dimm_bit_0 << endl; - out << " Max size of each bank queue: " << m_bank_queue_size << endl; - out << " Refresh period (within one bank): " << m_refresh_period << endl; - out << " Arbitration randomness: " << m_mem_random_arbitrate << endl; -} - -void RubyMemoryControl::clearStats() const { m_profiler_ptr->clearStats(); diff --git a/src/mem/ruby/system/RubyMemoryControl.hh b/src/mem/ruby/system/RubyMemoryControl.hh index af915c807..512533f97 100644 --- a/src/mem/ruby/system/RubyMemoryControl.hh +++ b/src/mem/ruby/system/RubyMemoryControl.hh @@ -81,10 +81,6 @@ class RubyMemoryControl : public MemoryControl bool isReady(); bool areNSlotsAvailable(int n) { return true; }; // infinite queue length - //// Called from L3 cache: - //void writeBack(physical_address_t addr); - - void printConfig(std::ostream& out); void print(std::ostream& out) const; void clearStats() const; void printStats(std::ostream& out) const; diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 8733ec514..a4cdca53f 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -201,16 +201,6 @@ Sequencer::printProgress(ostream& out) const #endif } -void -Sequencer::printConfig(ostream& out) const -{ - out << "Seqeuncer config: " << m_name << endl - << " controller: " << m_controller->getName() << endl - << " version: " << m_version << endl - << " max_outstanding_requests: " << m_max_outstanding_requests << endl - << " deadlock_threshold: " << m_deadlock_threshold << endl; -} - // Insert the request on the correct request table. Return true if // the entry was already present. RequestStatus diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 2778cf380..a912347aa 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -67,8 +67,6 @@ class Sequencer : public RubyPort, public Consumer // Public Methods void wakeup(); // Used only for deadlock detection - void printConfig(std::ostream& out) const; - void printProgress(std::ostream& out) const; void writeCallback(const Address& address, DataBlock& data); diff --git a/src/mem/ruby/system/SparseMemory.hh b/src/mem/ruby/system/SparseMemory.hh index e4237dbcd..143ed5c1e 100644 --- a/src/mem/ruby/system/SparseMemory.hh +++ b/src/mem/ruby/system/SparseMemory.hh @@ -54,8 +54,6 @@ class SparseMemory SparseMemory(int number_of_levels); ~SparseMemory(); - void printConfig(std::ostream& out) { } - bool exist(const Address& address) const; void add(const Address& address, AbstractEntry*); void remove(const Address& address); diff --git a/src/mem/ruby/system/System.cc b/src/mem/ruby/system/System.cc index abce74830..b06e8b7ed 100644 --- a/src/mem/ruby/system/System.cc +++ b/src/mem/ruby/system/System.cc @@ -139,29 +139,6 @@ RubySystem::~RubySystem() } void -RubySystem::printSystemConfig(ostream & out) -{ - out << "RubySystem config:" << endl - << " random_seed: " << m_random_seed << endl - << " randomization: " << m_randomization << endl - << " cycle_period: " << m_clock << endl - << " block_size_bytes: " << m_block_size_bytes << endl - << " block_size_bits: " << m_block_size_bits << endl - << " memory_size_bytes: " << m_memory_size_bytes << endl - << " memory_size_bits: " << m_memory_size_bits << endl; -} - -void -RubySystem::printConfig(ostream& out) -{ - out << "\n================ Begin RubySystem Configuration Print ================\n\n"; - printSystemConfig(out); - m_network_ptr->printConfig(out); - m_profiler_ptr->printConfig(out); - out << "\n================ End RubySystem Configuration Print ================\n\n"; -} - -void RubySystem::printStats(ostream& out) { const time_t T = time(NULL); @@ -488,7 +465,5 @@ void RubyExitCallback::process() { std::ostream *os = simout.create(stats_filename); - RubySystem::printConfig(*os); - *os << endl; RubySystem::printStats(*os); } diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh index 3d86c3e02..bbb14667f 100644 --- a/src/mem/ruby/system/System.hh +++ b/src/mem/ruby/system/System.hh @@ -107,7 +107,6 @@ class RubySystem : public SimObject return m_mem_vec_ptr; } - static void printConfig(std::ostream& out); static void printStats(std::ostream& out); void clearStats() const; diff --git a/src/mem/ruby/system/TBETable.hh b/src/mem/ruby/system/TBETable.hh index 022654bce..fa4493757 100644 --- a/src/mem/ruby/system/TBETable.hh +++ b/src/mem/ruby/system/TBETable.hh @@ -46,12 +46,6 @@ class TBETable { } - void - printConfig(std::ostream& out) - { - out << "TBEs_per_TBETable: " << m_number_of_TBEs << std::endl; - } - bool isPresent(const Address& address) const; void allocate(const Address& address); void deallocate(const Address& address); diff --git a/src/mem/ruby/system/TimerTable.hh b/src/mem/ruby/system/TimerTable.hh index 41b4ea68d..e4419d4d3 100644 --- a/src/mem/ruby/system/TimerTable.hh +++ b/src/mem/ruby/system/TimerTable.hh @@ -43,8 +43,6 @@ class TimerTable public: TimerTable(); - static void printConfig(std::ostream& out) {} - void setConsumer(Consumer* consumer_ptr) { diff --git a/src/mem/ruby/system/WireBuffer.cc b/src/mem/ruby/system/WireBuffer.cc index bab935c5d..f007d6c51 100644 --- a/src/mem/ruby/system/WireBuffer.cc +++ b/src/mem/ruby/system/WireBuffer.cc @@ -144,11 +144,6 @@ WireBuffer::print(ostream& out) const } void -WireBuffer::printConfig(ostream& out) -{ -} - -void WireBuffer::clearStats() const { } diff --git a/src/mem/ruby/system/WireBuffer.hh b/src/mem/ruby/system/WireBuffer.hh index 648019aeb..bc3afa2da 100644 --- a/src/mem/ruby/system/WireBuffer.hh +++ b/src/mem/ruby/system/WireBuffer.hh @@ -82,7 +82,6 @@ class WireBuffer : public SimObject bool isReady(); bool areNSlotsAvailable(int n) { return true; }; // infinite queue length - void printConfig(std::ostream& out); void print(std::ostream& out) const; void clearStats() const; void printStats(std::ostream& out) const; |