10 files changed, 28 insertions, 22 deletions
diff --git a/src/mem/ruby/system/Cache.py b/src/mem/ruby/system/Cache.py
index 4b0269822..d4af1320a 100644
--- a/src/mem/ruby/system/Cache.py
+++ b/src/mem/ruby/system/Cache.py
@@ -36,7 +36,7 @@ class RubyCache(SimObject):
     cxx_class = 'CacheMemory'
     cxx_header = "mem/ruby/system/CacheMemory.hh"
     size = Param.MemorySize("capacity in bytes");
-    latency = Param.Int("");
+    latency = Param.Cycles("");
     assoc = Param.Int("");
     replacement_policy = Param.String("PSEUDO_LRU", "");
     start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line");
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index a4950a09b..6b436082f 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -92,7 +92,7 @@ class CacheMemory : public SimObject
     AbstractCacheEntry* lookup(const Address& address);
     const AbstractCacheEntry* lookup(const Address& address) const;
 
-    int getLatency() const { return m_latency; }
+    Cycles getLatency() const { return m_latency; }
 
     // Hook for checkpointing the contents of the cache
     void recordCacheContents(int cntrl, CacheRecorder* tr) const;
@@ -144,7 +144,7 @@ class CacheMemory : public SimObject
 
   private:
     const std::string m_cache_name;
-    int m_latency;
+    Cycles m_latency;
 
     // Data Members (m_prefix)
     bool m_is_instruction_only_cache;
diff --git a/src/mem/ruby/system/RubyMemoryControl.cc b/src/mem/ruby/system/RubyMemoryControl.cc
index 620113719..121551299 100644
--- a/src/mem/ruby/system/RubyMemoryControl.cc
+++ b/src/mem/ruby/system/RubyMemoryControl.cc
@@ -374,10 +374,10 @@ RubyMemoryControl::printStats(ostream& out) const
 
 // Queue up a completed request to send back to directory
 void
-RubyMemoryControl::enqueueToDirectory(MemoryNode req, int latency)
+RubyMemoryControl::enqueueToDirectory(MemoryNode req, Cycles latency)
 {
     Time arrival_time = curTick() + (latency * clock);
-    Time ruby_arrival_time = arrival_time / g_system_ptr->clockPeriod();
+    Cycles ruby_arrival_time = g_system_ptr->ticksToCycles(arrival_time);
     req.m_time = ruby_arrival_time;
     m_response_queue.push_back(req);
 
diff --git a/src/mem/ruby/system/RubyMemoryControl.hh b/src/mem/ruby/system/RubyMemoryControl.hh
index 53e8fabef..bd94abaa6 100644
--- a/src/mem/ruby/system/RubyMemoryControl.hh
+++ b/src/mem/ruby/system/RubyMemoryControl.hh
@@ -100,7 +100,7 @@ class RubyMemoryControl : public MemoryControl
     uint32_t functionalWriteBuffers(Packet *pkt);
 
   private:
-    void enqueueToDirectory(MemoryNode req, int latency);
+    void enqueueToDirectory(MemoryNode req, Cycles latency);
     const int getRank(int bank) const;
     bool queueReady(int bank);
     void issueRequest(int bank);
@@ -128,11 +128,11 @@ class RubyMemoryControl : public MemoryControl
     int m_rank_rank_delay;
     int m_read_write_delay;
     int m_basic_bus_busy_time;
-    int m_mem_ctl_latency;
+    Cycles m_mem_ctl_latency;
     int m_refresh_period;
     int m_mem_random_arbitrate;
     int m_tFaw;
-    int m_mem_fixed_delay;
+    Cycles m_mem_fixed_delay;
 
     int m_total_banks;
     int m_total_ranks;
diff --git a/src/mem/ruby/system/RubyMemoryControl.py b/src/mem/ruby/system/RubyMemoryControl.py
index 7764938d3..e46b3f223 100644
--- a/src/mem/ruby/system/RubyMemoryControl.py
+++ b/src/mem/ruby/system/RubyMemoryControl.py
@@ -50,8 +50,8 @@ class RubyMemoryControl(MemoryControl):
     rank_rank_delay = Param.Int(1, "");
     read_write_delay = Param.Int(2, "");
     basic_bus_busy_time = Param.Int(2, "");
-    mem_ctl_latency = Param.Int(12, "");
-    refresh_period = Param.Int(1560, "");
+    mem_ctl_latency = Param.Cycles(12, "");
+    refresh_period = Param.Cycles(1560, "");
     tFaw = Param.Int(0, "");
     mem_random_arbitrate = Param.Int(0, "");
-    mem_fixed_delay = Param.Int(0, "");
+    mem_fixed_delay = Param.Cycles(0, "");
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 9b30fdbd5..d4cfe77b1 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -668,7 +668,7 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
             msg->getPhysicalAddress(),
             RubyRequestType_to_string(secondary_type));
 
-    Time latency = 0;  // initialzed to an null value
+    Cycles latency(0);  // initialzed to an null value
 
     if (secondary_type == RubyRequestType_IFETCH)
         latency = m_instCache_ptr->getLatency();
diff --git a/src/mem/ruby/system/TimerTable.cc b/src/mem/ruby/system/TimerTable.cc
index 992401c50..d87f11662 100644
--- a/src/mem/ruby/system/TimerTable.cc
+++ b/src/mem/ruby/system/TimerTable.cc
@@ -66,12 +66,13 @@ TimerTable::readyAddress() const
 }
 
 void
-TimerTable::set(const Address& address, Time relative_latency)
+TimerTable::set(const Address& address, Cycles relative_latency)
 {
     assert(address == line_address(address));
     assert(relative_latency > 0);
     assert(!m_map.count(address));
-    Time ready_time = m_clockobj_ptr->curCycle() + relative_latency;
+
+    Cycles ready_time = m_clockobj_ptr->curCycle() + relative_latency;
     m_map[address] = ready_time;
     assert(m_consumer_ptr != NULL);
     m_consumer_ptr->scheduleEventAbsolute(ready_time);
diff --git a/src/mem/ruby/system/TimerTable.hh b/src/mem/ruby/system/TimerTable.hh
index ecd95ee19..95af2eaa7 100644
--- a/src/mem/ruby/system/TimerTable.hh
+++ b/src/mem/ruby/system/TimerTable.hh
@@ -64,7 +64,10 @@ class TimerTable
     bool isReady() const;
     const Address& readyAddress() const;
     bool isSet(const Address& address) const { return !!m_map.count(address); }
-    void set(const Address& address, Time relative_latency);
+    void set(const Address& address, Cycles relative_latency);
+    void set(const Address& address, uint64_t relative_latency)
+    { set(address, Cycles(relative_latency)); }
+
     void unset(const Address& address);
     void print(std::ostream& out) const;
 
@@ -79,7 +82,7 @@ class TimerTable
 
     // use a std::map for the address map as this container is sorted
     // and ensures a well-defined iteration order
-    typedef std::map<Address, Time> AddressMap;
+    typedef std::map<Address, Cycles> AddressMap;
     AddressMap m_map;
     mutable bool m_next_valid;
     mutable Time m_next_time; // Only valid if m_next_valid is true
diff --git a/src/mem/ruby/system/WireBuffer.cc b/src/mem/ruby/system/WireBuffer.cc
index b5a2849ce..fba53b902 100644
--- a/src/mem/ruby/system/WireBuffer.cc
+++ b/src/mem/ruby/system/WireBuffer.cc
@@ -70,12 +70,13 @@ WireBuffer::~WireBuffer()
 }
 
 void
-WireBuffer::enqueue(MsgPtr message, int latency)
+WireBuffer::enqueue(MsgPtr message, Cycles latency)
 {
     m_msg_counter++;
-    Time current_time = g_system_ptr->getTime();
-    Time arrival_time = current_time + latency;
+    Cycles current_time = g_system_ptr->getTime();
+    Cycles arrival_time = current_time + latency;
     assert(arrival_time > current_time);
+
     MessageBufferNode thisNode(arrival_time, m_msg_counter, message);
     m_message_queue.push_back(thisNode);
     if (m_consumer_ptr != NULL) {
@@ -122,11 +123,12 @@ WireBuffer::recycle()
     MessageBufferNode node = m_message_queue.front();
     pop_heap(m_message_queue.begin(), m_message_queue.end(),
         greater<MessageBufferNode>());
-    node.m_time = g_system_ptr->getTime() + 1;
+
+    node.m_time = g_system_ptr->getTime() + Cycles(1);
     m_message_queue.back() = node;
     push_heap(m_message_queue.begin(), m_message_queue.end(),
         greater<MessageBufferNode>());
-    m_consumer_ptr->scheduleEventAbsolute(g_system_ptr->getTime() + 1);
+    m_consumer_ptr->scheduleEventAbsolute(node.m_time);
 }
 
 bool
diff --git a/src/mem/ruby/system/WireBuffer.hh b/src/mem/ruby/system/WireBuffer.hh
index 07da965c8..d71bf4520 100644
--- a/src/mem/ruby/system/WireBuffer.hh
+++ b/src/mem/ruby/system/WireBuffer.hh
@@ -72,7 +72,7 @@ class WireBuffer : public SimObject
     void setDescription(const std::string& name) { m_description = name; };
     std::string getDescription() { return m_description; };
 
-    void enqueue(MsgPtr message, int latency );
+    void enqueue(MsgPtr message, Cycles latency);
     void dequeue();
     const Message* peek();
     MessageBufferNode peekNode();