diff options
Diffstat (limited to 'src/mem/ruby/system')
| -rw-r--r-- | src/mem/ruby/system/AbstractMemOrCache.hh | 1 | ||||
| -rw-r--r-- | src/mem/ruby/system/CacheMemory.hh | 96 | ||||
| -rw-r--r-- | src/mem/ruby/system/DMASequencer.cc | 37 | ||||
| -rw-r--r-- | src/mem/ruby/system/DMASequencer.hh | 1 | ||||
| -rw-r--r-- | src/mem/ruby/system/DirectoryMemory.cc | 1 | ||||
| -rw-r--r-- | src/mem/ruby/system/PerfectCacheMemory.hh | 1 | ||||
| -rw-r--r-- | src/mem/ruby/system/ProcessorInterface.hh | 45 | ||||
| -rw-r--r-- | src/mem/ruby/system/Sequencer.cc | 180 | ||||
| -rw-r--r-- | src/mem/ruby/system/Sequencer.hh | 1 | ||||
| -rw-r--r-- | src/mem/ruby/system/System.cc | 31 | ||||
| -rw-r--r-- | src/mem/ruby/system/System.hh | 14 |
11 files changed, 66 insertions, 342 deletions
diff --git a/src/mem/ruby/system/AbstractMemOrCache.hh b/src/mem/ruby/system/AbstractMemOrCache.hh index 641c117de..845ce66ea 100644 --- a/src/mem/ruby/system/AbstractMemOrCache.hh +++ b/src/mem/ruby/system/AbstractMemOrCache.hh @@ -11,7 +11,6 @@ #define ABSTRACT_MEM_OR_CACHE_H #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" class AbstractMemOrCache { diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh index 625d5ce59..cfaa229a5 100644 --- a/src/mem/ruby/system/CacheMemory.hh +++ b/src/mem/ruby/system/CacheMemory.hh @@ -52,6 +52,8 @@ #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" #include "mem/ruby/system/System.hh" #include "mem/ruby/slicc_interface/AbstractController.hh" +#include "mem/ruby/profiler/CacheProfiler.hh" +#include "mem/protocol/CacheMsg.hh" #include <vector> class CacheMemory { @@ -111,6 +113,8 @@ public: // Set this address to most recently used void setMRU(const Address& address); + void profileMiss(const CacheMsg & msg); + void getMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes ); void setMemoryValue(const Address& addr, char* value, @@ -123,6 +127,8 @@ public: void print(ostream& out) const; void printData(ostream& out) const; + void printStats(ostream& out) const; + private: // Private Methods @@ -154,51 +160,15 @@ private: AbstractReplacementPolicy *m_replacementPolicy_ptr; + CacheProfiler* m_profiler_ptr; + int m_cache_num_sets; int m_cache_num_set_bits; int m_cache_assoc; static Vector< CacheMemory* > m_all_caches; }; -/* -inline -CacheMemory* CacheMemory::getCache(int cache_id) -{ - assert(cache_id < RubyConfig::getNumberOfCaches()); - if (m_all_caches[cache_id] == NULL) { - cerr << "ERROR: Tried to obtain CacheMemory that hasn't been created yet." << endl; - assert(0); - } - return m_all_caches[cache_id]; -} - -inline -CacheMemory* CacheMemory::createCache(int level, int num, char split_type_c, AbstractCacheEntry* (*entry_factory)()) -{ - string split_type; - switch(split_type_c) { - case 'i': - split_type = "instruction"; break; - case 'd': - split_type = "data"; break; - default: - split_type = "unified"; break; - } - int cache_id = RubyConfig::getCacheIDFromParams(level, num, split_type); - assert(cache_id < RubyConfig::getNumberOfCaches()); - if (m_all_caches.size() == 0) { - m_all_caches.setSize(RubyConfig::getNumberOfCaches()); - for (int i=0; i<m_all_caches.size(); i++) - m_all_caches[i] = NULL; - } - string type = RubyConfig::getCacheType(cache_id); - if ( type == "SetAssociativeCache" ) { - m_all_caches[cache_id] = new CacheMemory(cache_id, entry_factory); - } - return m_all_caches[cache_id]; -} -*/ // Output operator declaration //ostream& operator<<(ostream& out, const CacheMemory<ENTRY>& obj); @@ -220,6 +190,7 @@ inline CacheMemory::CacheMemory(const string & name) : m_cache_name(name) { + m_profiler_ptr = new CacheProfiler(name); } inline @@ -266,43 +237,7 @@ void CacheMemory::init(const vector<string> & argv) } } } -/* -inline -CacheMemory::CacheMemory(int cache_id, AbstractCacheEntry* (*entry_factory)()) -{ - string split_type; - - m_cache_id = cache_id; - m_entry_factory = entry_factory; - - m_cache_num_set_bits = RubyConfig::getNumberOfCacheSetBits(cache_id); - m_cache_num_sets = RubyConfig::getNumberOfCacheSets(cache_id); - m_cache_assoc = RubyConfig::getCacheAssoc(cache_id); - split_type = RubyConfig::getCacheSplitType(cache_id); - m_is_instruction_only_cache = m_is_data_only_cache = false; - if (split_type == "instruction") - m_is_instruction_only_cache = true; - else if (split_type == "data") - m_is_data_only_cache = true; - else - assert(split_type == "unified"); - if(RubyConfig::getCacheReplacementPolicy(cache_id) == "PSEUDO_LRU") - m_replacementPolicy_ptr = new PseudoLRUPolicy(m_cache_num_sets, m_cache_assoc); - else if(RubyConfig::getCacheReplacementPolicy(cache_id) == "LRU") - m_replacementPolicy_ptr = new LRUPolicy(m_cache_num_sets, m_cache_assoc); - else - assert(false); - - m_cache.setSize(m_cache_num_sets); - for (int i = 0; i < m_cache_num_sets; i++) { - m_cache[i].setSize(m_cache_assoc); - for (int j = 0; j < m_cache_assoc; j++) { - m_cache[i][j] = m_entry_factory(); - } - } -} -*/ inline CacheMemory::~CacheMemory() { @@ -570,6 +505,13 @@ void CacheMemory::setMRU(const Address& address) } inline +void CacheMemory::profileMiss(const CacheMsg & msg) +{ + m_profiler_ptr->addStatSample(msg.getType(), msg.getAccessMode(), + msg.getSize(), msg.getPrefetch()); +} + +inline void CacheMemory::recordCacheContents(CacheRecorder& tr) const { for (int i = 0; i < m_cache_num_sets; i++) { @@ -620,6 +562,12 @@ void CacheMemory::printData(ostream& out) const } inline +void CacheMemory::printStats(ostream& out) const +{ + m_profiler_ptr->printStats(out); +} + +inline void CacheMemory::getMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes ){ AbstractCacheEntry& entry = lookup(line_address(addr)); diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc index 8f7b1c912..58ec7bb45 100644 --- a/src/mem/ruby/system/DMASequencer.cc +++ b/src/mem/ruby/system/DMASequencer.cc @@ -29,6 +29,7 @@ void DMASequencer::init(const vector<string> & argv) m_mandatory_q_ptr = m_controller->getMandatoryQueue(); m_is_busy = false; + m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits()); } int64_t DMASequencer::makeRequest(const RubyRequest & request) @@ -53,7 +54,7 @@ int64_t DMASequencer::makeRequest(const RubyRequest & request) assert(0); } - assert(!m_is_busy); + assert(!m_is_busy); // only support one outstanding DMA request m_is_busy = true; active_request.start_paddr = paddr; @@ -66,14 +67,15 @@ int64_t DMASequencer::makeRequest(const RubyRequest & request) DMARequestMsg msg; msg.getPhysicalAddress() = Address(paddr); + msg.getLineAddress() = line_address(msg.getPhysicalAddress()); msg.getType() = write ? DMARequestType_WRITE : DMARequestType_READ; - msg.getOffset() = paddr & RubyConfig::dataBlockMask(); - msg.getLen() = (msg.getOffset() + len) < RubySystem::getBlockSizeBytes() ? - (msg.getOffset() + len) : + msg.getOffset() = paddr & m_data_block_mask; + msg.getLen() = (msg.getOffset() + len) <= RubySystem::getBlockSizeBytes() ? + len : RubySystem::getBlockSizeBytes() - msg.getOffset(); if (write) { msg.getType() = DMARequestType_WRITE; - msg.getDataBlk().setData(data, 0, msg.getLen()); + msg.getDataBlk().setData(data, msg.getOffset(), msg.getLen()); } else { msg.getType() = DMARequestType_READ; } @@ -94,15 +96,20 @@ void DMASequencer::issueNext() } DMARequestMsg msg; - msg.getPhysicalAddress() = Address(active_request.start_paddr + active_request.bytes_completed); - assert((msg.getPhysicalAddress().getAddress() & RubyConfig::dataBlockMask()) == 0); + msg.getPhysicalAddress() = Address(active_request.start_paddr + + active_request.bytes_completed); + assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0); + msg.getLineAddress() = line_address(msg.getPhysicalAddress()); msg.getOffset() = 0; - msg.getType() = active_request.write ? DMARequestType_WRITE : DMARequestType_READ; - msg.getLen() = active_request.len - active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? - active_request.len - active_request.bytes_completed : - RubySystem::getBlockSizeBytes(); + msg.getType() = (active_request.write ? DMARequestType_WRITE : + DMARequestType_READ); + msg.getLen() = (active_request.len - + active_request.bytes_completed < RubySystem::getBlockSizeBytes() ? + active_request.len - active_request.bytes_completed : + RubySystem::getBlockSizeBytes()); if (active_request.write) { - msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed], 0, msg.getLen()); + msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed], + 0, msg.getLen()); msg.getType() = DMARequestType_WRITE; } else { msg.getType() = DMARequestType_READ; @@ -117,8 +124,10 @@ void DMASequencer::dataCallback(const DataBlock & dblk) int len = active_request.bytes_issued - active_request.bytes_completed; int offset = 0; if (active_request.bytes_completed == 0) - offset = active_request.start_paddr & RubyConfig::dataBlockMask(); - memcpy(&active_request.data[active_request.bytes_completed], dblk.getData(offset, len), len); + offset = active_request.start_paddr & m_data_block_mask; + assert( active_request.write == false ); + memcpy(&active_request.data[active_request.bytes_completed], + dblk.getData(offset, len), len); issueNext(); } diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh index 2665549e3..1f60b95ec 100644 --- a/src/mem/ruby/system/DMASequencer.hh +++ b/src/mem/ruby/system/DMASequencer.hh @@ -41,6 +41,7 @@ private: int m_version; AbstractController* m_controller; bool m_is_busy; + uint64_t m_data_block_mask; DMARequest active_request; int num_active_requests; MessageBuffer* m_mandatory_q_ptr; diff --git a/src/mem/ruby/system/DirectoryMemory.cc b/src/mem/ruby/system/DirectoryMemory.cc index 294d57de2..b279d21af 100644 --- a/src/mem/ruby/system/DirectoryMemory.cc +++ b/src/mem/ruby/system/DirectoryMemory.cc @@ -39,7 +39,6 @@ #include "mem/ruby/system/System.hh" #include "mem/ruby/system/DirectoryMemory.hh" #include "mem/ruby/slicc_interface/RubySlicc_Util.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/slicc_interface/AbstractController.hh" #include "mem/gems_common/util.hh" diff --git a/src/mem/ruby/system/PerfectCacheMemory.hh b/src/mem/ruby/system/PerfectCacheMemory.hh index 9d647822c..90c9273e5 100644 --- a/src/mem/ruby/system/PerfectCacheMemory.hh +++ b/src/mem/ruby/system/PerfectCacheMemory.hh @@ -42,7 +42,6 @@ #include "mem/ruby/common/Global.hh" #include "mem/gems_common/Map.hh" #include "mem/protocol/AccessPermission.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/slicc_interface/AbstractChip.hh" diff --git a/src/mem/ruby/system/ProcessorInterface.hh b/src/mem/ruby/system/ProcessorInterface.hh deleted file mode 100644 index d76e29f65..000000000 --- a/src/mem/ruby/system/ProcessorInterface.hh +++ /dev/null @@ -1,45 +0,0 @@ - -struct ProcessorRequest { - vector<CacheRequest*> cache_requests; -}; - -class ProcessorInterface { - -public: - - void read_atomic(const Address & paddr, void* data, int len) { - assert(paddr.getLineAddress() + RubyConfig::dataBlockBytes() >= paddr + len); - // for now, atomics can't span two blocks. Maybe fix this later - } - - void read(const Address & paddr, const Address & rip, AccessModeType atype, void* data, const int len) { - - // create the CacheRequests - ProcessorRequest* this_request = new ProcessorRequest; - Address split_addr = paddr; - int len_remaining = len; - while (split_addr.getAddress() < paddr.getAddress() + len) { - int split_len = (split_addr.getAddress() + len_remaining <= split_addr.getLineAddress() + RubyConfig::dataBlockBytes()) ? - len_remaining : - RubyConfig::dataBlockBytes() - split_addr.getOffset(); - CacheRequest creq = new CacheRequest( line_address(split_addr), - split_addr, - CacheRequestType_LD, - rip, - atype, - split_len, - PretchBit_No, - laddr, - 0); // SMT thread id); - this_request->cache_requests.push_back(creq); - split_addr += split_len; - len_remaining -= split_len; - } - outstanding_requests.push_back(this_request); - - } - -private: - vector<ProcessorRequest*> outstanding_requests; - Sequencer* m_sequencer; -}; diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 1587aa5fa..693e931aa 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -490,183 +490,3 @@ void Sequencer::checkCoherence(const Address& addr) { #endif } -/* -bool Sequencer::getRubyMemoryValue(const Address& addr, char* value, - unsigned int size_in_bytes ) -{ - bool found = false; - const Address lineAddr = line_address(addr); - DataBlock data; - PhysAddress paddr(addr); - DataBlock* dataPtr = &data; - - MachineID l2_mach = map_L2ChipId_to_L2Cache(addr, m_chip_ptr->getID() ); - int l2_ver = l2_mach.num%RubyConfig::numberOfL2CachePerChip(); - - if (Protocol::m_TwoLevelCache) { - if(Protocol::m_CMP){ - assert(n->m_L2Cache_L2cacheMemory_vec[l2_ver] != NULL); - } - else{ - assert(n->m_L1Cache_cacheMemory_vec[m_version] != NULL); - } - } - - if (n->m_L1Cache_L1IcacheMemory_vec[m_version]->tryCacheAccess(lineAddr, CacheRequestType_IFETCH, dataPtr)){ - n->m_L1Cache_L1IcacheMemory_vec[m_version]->getMemoryValue(addr, value, size_in_bytes); - found = true; - } else if (n->m_L1Cache_L1DcacheMemory_vec[m_version]->tryCacheAccess(lineAddr, CacheRequestType_LD, dataPtr)){ - n->m_L1Cache_L1DcacheMemory_vec[m_version]->getMemoryValue(addr, value, size_in_bytes); - found = true; - } else if (Protocol::m_CMP && n->m_L2Cache_L2cacheMemory_vec[l2_ver]->tryCacheAccess(lineAddr, CacheRequestType_LD, dataPtr)){ - n->m_L2Cache_L2cacheMemory_vec[l2_ver]->getMemoryValue(addr, value, size_in_bytes); - found = true; - // } else if (n->TBE_TABLE_MEMBER_VARIABLE->isPresent(lineAddr)){ -// ASSERT(n->TBE_TABLE_MEMBER_VARIABLE->isPresent(lineAddr)); -// L1Cache_TBE tbeEntry = n->TBE_TABLE_MEMBER_VARIABLE->lookup(lineAddr); - -// int offset = addr.getOffset(); -// for(int i=0; i<size_in_bytes; ++i){ -// value[i] = tbeEntry.getDataBlk().getByte(offset + i); -// } - -// found = true; - } else { - // Address not found - //cout << " " << m_chip_ptr->getID() << " NOT IN CACHE, Value at Directory is: " << (int) value[0] << endl; - n = dynamic_cast<Chip*>(g_system_ptr->getChip(map_Address_to_DirectoryNode(addr)/RubyConfig::numberOfDirectoryPerChip())); - int dir_version = map_Address_to_DirectoryNode(addr)%RubyConfig::numberOfDirectoryPerChip(); - for(unsigned int i=0; i<size_in_bytes; ++i){ - int offset = addr.getOffset(); - value[i] = n->m_Directory_directory_vec[dir_version]->lookup(lineAddr).m_DataBlk.getByte(offset + i); - } - // Address not found - //WARN_MSG("Couldn't find address"); - //WARN_EXPR(addr); - found = false; - } - return true; -} - -bool Sequencer::setRubyMemoryValue(const Address& addr, char *value, - unsigned int size_in_bytes) { - char test_buffer[64]; - - // idea here is that coherent cache should find the - // latest data, the update it - bool found = false; - const Address lineAddr = line_address(addr); - PhysAddress paddr(addr); - DataBlock data; - DataBlock* dataPtr = &data; - Chip* n = dynamic_cast<Chip*>(m_chip_ptr); - - MachineID l2_mach = map_L2ChipId_to_L2Cache(addr, m_chip_ptr->getID() ); - int l2_ver = l2_mach.num%RubyConfig::numberOfL2CachePerChip(); - - assert(n->m_L1Cache_L1IcacheMemory_vec[m_version] != NULL); - assert(n->m_L1Cache_L1DcacheMemory_vec[m_version] != NULL); - if (Protocol::m_TwoLevelCache) { - if(Protocol::m_CMP){ - assert(n->m_L2Cache_L2cacheMemory_vec[l2_ver] != NULL); - } - else{ - assert(n->m_L1Cache_cacheMemory_vec[m_version] != NULL); - } - } - - if (n->m_L1Cache_L1IcacheMemory_vec[m_version]->tryCacheAccess(lineAddr, CacheRequestType_IFETCH, dataPtr)){ - n->m_L1Cache_L1IcacheMemory_vec[m_version]->setMemoryValue(addr, value, size_in_bytes); - found = true; - } else if (n->m_L1Cache_L1DcacheMemory_vec[m_version]->tryCacheAccess(lineAddr, CacheRequestType_LD, dataPtr)){ - n->m_L1Cache_L1DcacheMemory_vec[m_version]->setMemoryValue(addr, value, size_in_bytes); - found = true; - } else if (Protocol::m_CMP && n->m_L2Cache_L2cacheMemory_vec[l2_ver]->tryCacheAccess(lineAddr, CacheRequestType_LD, dataPtr)){ - n->m_L2Cache_L2cacheMemory_vec[l2_ver]->setMemoryValue(addr, value, size_in_bytes); - found = true; - } else { - // Address not found - n = dynamic_cast<Chip*>(g_system_ptr->getChip(map_Address_to_DirectoryNode(addr)/RubyConfig::numberOfDirectoryPerChip())); - int dir_version = map_Address_to_DirectoryNode(addr)%RubyConfig::numberOfDirectoryPerChip(); - for(unsigned int i=0; i<size_in_bytes; ++i){ - int offset = addr.getOffset(); - n->m_Directory_directory_vec[dir_version]->lookup(lineAddr).m_DataBlk.setByte(offset + i, value[i]); - } - found = false; - } - - if (found){ - found = getRubyMemoryValue(addr, test_buffer, size_in_bytes); - assert(found); - if(value[0] != test_buffer[0]){ - WARN_EXPR((int) value[0]); - WARN_EXPR((int) test_buffer[0]); - ERROR_MSG("setRubyMemoryValue failed to set value."); - } - } - - return true; -} -*/ -/* - -void -Sequencer::rubyMemAccess(const uint64 paddr, char* data, const int len, const AccessType type) -{ - if ( type == AccessType_Read || type == AccessType_Write ) { - // need to break up the packet data - uint64 guest_ptr = paddr; - Vector<DataBlock*> datablocks; - while (paddr + len != guest_ptr) { - Address addr(guest_ptr); - Address line_addr = line_address(addr); - - int bytes_copied; - if (addr.getOffset() == 0) { - bytes_copied = (guest_ptr + RubyConfig::dataBlockBytes() > paddr + len)? - (paddr + len - guest_ptr): - RubyConfig::dataBlockBytes(); - } else { - bytes_copied = RubyConfig::dataBlockBytes() - addr.getOffset(); - if (guest_ptr + bytes_copied > paddr + len) - bytes_copied = paddr + len - guest_ptr; - } - - // first we need to find all data blocks that have to be updated for a write - // and the highest block for a read - for(int i=0;i<RubyConfig::numberOfProcessors();i++) { - if (Protocol::m_TwoLevelCache){ - if(m_chip_ptr->m_L1Cache_L1IcacheMemory_vec[i]->isTagPresent(line_address(addr))) - datablocks.insertAtBottom(&m_chip_ptr->m_L1Cache_L1IcacheMemory_vec[i]->lookup(line_addr).getDataBlk()); - if(m_chip_ptr->m_L1Cache_L1DcacheMemory_vec[i]->isTagPresent(line_address(addr))) - datablocks.insertAtBottom(&m_chip_ptr->m_L1Cache_L1DcacheMemory_vec[i]->lookup(line_addr).getDataBlk()); - } else { - if(m_chip_ptr->m_L1Cache_cacheMemory_vec[i]->isTagPresent(line_address(addr))) - datablocks.insertAtBottom(&m_chip_ptr->m_L1Cache_cacheMemory_vec[i]->lookup(line_addr).getDataBlk()); - } - } - if (Protocol::m_TwoLevelCache){ - int l2_bank = map_L2ChipId_to_L2Cache(addr, 0).num; // TODO: ONLY WORKS WITH CMP!!! - if (m_chip_ptr->m_L2Cache_L2cacheMemory_vec[l2_bank]->isTagPresent(line_address(Address(paddr)))) { - datablocks.insertAtBottom(&m_chip_ptr->m_L2Cache_L2cacheMemory_vec[l2_bank]->lookup(addr).getDataBlk()); - } - } - assert(dynamic_cast<Chip*>(m_chip_ptr)->m_Directory_directory_vec.size() > map_Address_to_DirectoryNode(addr)); - DirectoryMemory* dir = dynamic_cast<Chip*>(m_chip_ptr)->m_Directory_directory_vec[map_Address_to_DirectoryNode(addr)]; - Directory_Entry& entry = dir->lookup(line_addr); - datablocks.insertAtBottom(&entry.getDataBlk()); - - if (pkt->isRead()){ - datablocks[0]->copyData(pkt_data, addr.getOffset(), bytes_copied); - } else {// pkt->isWrite() { - for (int i=0;i<datablocks.size();i++) - datablocks[i]->setData(pkt_data, addr.getOffset(), bytes_copied); - } - - guest_ptr += bytes_copied; - pkt_data += bytes_copied; - datablocks.clear(); - } -} - -*/ diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 254f5a092..9b55e9781 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -38,7 +38,6 @@ #define SEQUENCER_H #include "mem/ruby/common/Global.hh" -#include "mem/ruby/config/RubyConfig.hh" #include "mem/ruby/common/Consumer.hh" #include "mem/protocol/CacheRequestType.hh" #include "mem/protocol/AccessModeType.hh" diff --git a/src/mem/ruby/system/System.cc b/src/mem/ruby/system/System.cc index e922d0bbf..2c24c9ade 100644 --- a/src/mem/ruby/system/System.cc +++ b/src/mem/ruby/system/System.cc @@ -278,16 +278,7 @@ RubySystem::RubySystem(const vector <RubyObjConf> & sys_conf) RubySystem::~RubySystem() { - /* - for (int i=0; i < MachineType_base_level(MachineType_NUM); i++) { - for (int j=0; j < RubyConfig::getNumberOfControllersPerType(i); j++ ) { - delete m_controllers[i][j]; - } - } - delete m_network_ptr; - delete m_profiler_ptr; - delete m_tracer_ptr; - */ + } void RubySystem::printSystemConfig(ostream & out) @@ -307,8 +298,6 @@ void RubySystem::printSystemConfig(ostream & out) void RubySystem::printConfig(ostream& out) { out << "\n================ Begin RubySystem Configuration Print ================\n\n"; - // RubyConfig::printConfiguration(out); - // out << endl; printSystemConfig(out); for (map<string, AbstractController*>::const_iterator it = m_controllers.begin(); it != m_controllers.end(); it++) { @@ -346,6 +335,10 @@ void RubySystem::printStats(ostream& out) m_profiler_ptr->printStats(out); m_network_ptr->printStats(out); + for (map<string, CacheMemory*>::const_iterator it = m_caches.begin(); + it != m_caches.end(); it++) { + (*it).second->printStats(out); + } for (map<string, AbstractController*>::const_iterator it = m_controllers.begin(); it != m_controllers.end(); it++) { (*it).second->printStats(out); @@ -367,19 +360,7 @@ void RubySystem::clearStats() const void RubySystem::recordCacheContents(CacheRecorder& tr) const { - /* - for (int i = 0; i < m_chip_vector.size(); i++) { - for (int m_version = 0; m_version < RubyConfig::numberOfProcsPerChip(); m_version++) { - if (Protocol::m_TwoLevelCache) { - m_chip_vector[i]->m_L1Cache_L1IcacheMemory_vec[m_version]->setAsInstructionCache(true); - m_chip_vector[i]->m_L1Cache_L1DcacheMemory_vec[m_version]->setAsInstructionCache(false); - } else { - m_chip_vector[i]->m_L1Cache_cacheMemory_vec[m_version]->setAsInstructionCache(false); - } - } - m_chip_vector[i]->recordCacheContents(tr); - } - */ + } #ifdef CHECK_COHERENCE diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh index 8cbeb2b0e..dbf4dbc78 100644 --- a/src/mem/ruby/system/System.hh +++ b/src/mem/ruby/system/System.hh @@ -61,6 +61,20 @@ class DirectoryMemory; class Topology; class MemoryControl; +/* + * This defines the number of longs (32-bits on 32 bit machines, + * 64-bit on 64-bit AMD machines) to use to hold the set... + * the default is 4, allowing 128 or 256 different members + * of the set. + * + * This should never need to be changed for correctness reasons, + * though increasing it will increase performance for larger + * set sizes at the cost of a (much) larger memory footprint + * + */ +const int NUMBER_WORDS_PER_SET = 4; + + struct RubyObjConf { string type; string name; |