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-rw-r--r--src/mem/ruby/system/AbstractReplacementPolicy.hh2
-rw-r--r--src/mem/ruby/system/Cache.py1
-rw-r--r--src/mem/ruby/system/CacheMemory.cc1
-rw-r--r--src/mem/ruby/system/DMASequencer.cc1
-rw-r--r--src/mem/ruby/system/DirectoryMemory.cc44
-rw-r--r--src/mem/ruby/system/DirectoryMemory.hh9
-rw-r--r--src/mem/ruby/system/MemoryControl.cc3
-rw-r--r--src/mem/ruby/system/MemoryControl.hh3
-rw-r--r--src/mem/ruby/system/PersistentTable.hh1
-rw-r--r--src/mem/ruby/system/SConscript2
-rw-r--r--src/mem/ruby/system/Sequencer.cc10
-rw-r--r--src/mem/ruby/system/SparseMemory.cc35
-rw-r--r--src/mem/ruby/system/SparseMemory.hh6
-rw-r--r--src/mem/ruby/system/System.hh13
14 files changed, 56 insertions, 75 deletions
diff --git a/src/mem/ruby/system/AbstractReplacementPolicy.hh b/src/mem/ruby/system/AbstractReplacementPolicy.hh
index 3ddf4ab60..d03685c65 100644
--- a/src/mem/ruby/system/AbstractReplacementPolicy.hh
+++ b/src/mem/ruby/system/AbstractReplacementPolicy.hh
@@ -29,7 +29,7 @@
#ifndef __MEM_RUBY_SYSTEM_ABSTRACTREPLACEMENTPOLICY_HH__
#define __MEM_RUBY_SYSTEM_ABSTRACTREPLACEMENTPOLICY_HH__
-#include "mem/ruby/common/Global.hh"
+#include "mem/ruby/common/TypeDefines.hh"
class AbstractReplacementPolicy
{
diff --git a/src/mem/ruby/system/Cache.py b/src/mem/ruby/system/Cache.py
index ab3ec4b29..79ab9b070 100644
--- a/src/mem/ruby/system/Cache.py
+++ b/src/mem/ruby/system/Cache.py
@@ -39,3 +39,4 @@ class RubyCache(SimObject):
assoc = Param.Int("");
replacement_policy = Param.String("PSEUDO_LRU", "");
start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line");
+ is_icache = Param.Bool(False, "is instruction only cache");
diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
index fbf303ed8..1564128d3 100644
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -55,6 +55,7 @@ CacheMemory::CacheMemory(const Params *p)
m_policy = p->replacement_policy;
m_profiler_ptr = new CacheProfiler(name());
m_start_index_bit = p->start_index_bit;
+ m_is_instruction_only_cache = p->is_icache;
}
void
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 0e82ba3eb..763eb586a 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -30,7 +30,6 @@
#include "mem/protocol/SequencerMsg.hh"
#include "mem/protocol/SequencerRequestType.hh"
#include "mem/ruby/buffers/MessageBuffer.hh"
-#include "mem/ruby/slicc_interface/AbstractController.hh"
#include "mem/ruby/system/DMASequencer.hh"
#include "mem/ruby/system/System.hh"
diff --git a/src/mem/ruby/system/DirectoryMemory.cc b/src/mem/ruby/system/DirectoryMemory.cc
index a91f05a69..03aa68919 100644
--- a/src/mem/ruby/system/DirectoryMemory.cc
+++ b/src/mem/ruby/system/DirectoryMemory.cc
@@ -59,7 +59,7 @@ DirectoryMemory::init()
if (m_use_map) {
m_sparseMemory = new SparseMemory(m_map_levels);
} else {
- m_entries = new Directory_Entry*[m_num_entries];
+ m_entries = new AbstractEntry*[m_num_entries];
for (int i = 0; i < m_num_entries; i++)
m_entries[i] = NULL;
m_ram = g_system_ptr->getMemoryVector();
@@ -150,38 +150,40 @@ DirectoryMemory::mapAddressToLocalIdx(PhysAddress address)
return ret >> (RubySystem::getBlockSizeBits());
}
-Directory_Entry&
+AbstractEntry*
DirectoryMemory::lookup(PhysAddress address)
{
assert(isPresent(address));
- Directory_Entry* entry;
+ DPRINTF(RubyCache, "Looking up address: %s\n", address);
+
+ if (m_use_map) {
+ return m_sparseMemory->lookup(address);
+ } else {
+ uint64_t idx = mapAddressToLocalIdx(address);
+ assert(idx < m_num_entries);
+ return m_entries[idx];
+ }
+}
+
+AbstractEntry*
+DirectoryMemory::allocate(const PhysAddress& address, AbstractEntry* entry)
+{
+ assert(isPresent(address));
uint64 idx;
DPRINTF(RubyCache, "Looking up address: %s\n", address);
if (m_use_map) {
- if (m_sparseMemory->exist(address)) {
- entry = m_sparseMemory->lookup(address);
- assert(entry != NULL);
- } else {
- // Note: SparseMemory internally creates a new Directory Entry
- m_sparseMemory->add(address);
- entry = m_sparseMemory->lookup(address);
- entry->changePermission(AccessPermission_Read_Write);
- }
+ m_sparseMemory->add(address, entry);
+ entry->changePermission(AccessPermission_Read_Write);
} else {
idx = mapAddressToLocalIdx(address);
assert(idx < m_num_entries);
- entry = m_entries[idx];
-
- if (entry == NULL) {
- entry = new Directory_Entry();
- entry->getDataBlk().assign(m_ram->getBlockPtr(address));
- entry->changePermission(AccessPermission_Read_Only);
- m_entries[idx] = entry;
- }
+ entry->getDataBlk().assign(m_ram->getBlockPtr(address));
+ entry->changePermission(AccessPermission_Read_Only);
+ m_entries[idx] = entry;
}
- return *entry;
+ return entry;
}
void
diff --git a/src/mem/ruby/system/DirectoryMemory.hh b/src/mem/ruby/system/DirectoryMemory.hh
index 79b04726a..1b4d09b8e 100644
--- a/src/mem/ruby/system/DirectoryMemory.hh
+++ b/src/mem/ruby/system/DirectoryMemory.hh
@@ -32,9 +32,8 @@
#include <iostream>
#include <string>
-#include "mem/protocol/Directory_Entry.hh"
#include "mem/ruby/common/Address.hh"
-#include "mem/ruby/common/Global.hh"
+#include "mem/ruby/slicc_interface/AbstractEntry.hh"
#include "mem/ruby/system/MemoryVector.hh"
#include "mem/ruby/system/SparseMemory.hh"
#include "params/RubyDirectoryMemory.hh"
@@ -58,7 +57,9 @@ class DirectoryMemory : public SimObject
void printConfig(std::ostream& out) const;
static void printGlobalConfig(std::ostream & out);
bool isPresent(PhysAddress address);
- Directory_Entry& lookup(PhysAddress address);
+ AbstractEntry* lookup(PhysAddress address);
+ AbstractEntry* allocate(const PhysAddress& address,
+ AbstractEntry* new_entry);
void invalidateBlock(PhysAddress address);
@@ -72,7 +73,7 @@ class DirectoryMemory : public SimObject
private:
const std::string m_name;
- Directory_Entry **m_entries;
+ AbstractEntry **m_entries;
// int m_size; // # of memory module blocks this directory is
// responsible for
uint64 m_size_bytes;
diff --git a/src/mem/ruby/system/MemoryControl.cc b/src/mem/ruby/system/MemoryControl.cc
index eb27c0f78..2ab0736e5 100644
--- a/src/mem/ruby/system/MemoryControl.cc
+++ b/src/mem/ruby/system/MemoryControl.cc
@@ -104,8 +104,8 @@
*
*/
+#include "base/cast.hh"
#include "base/cprintf.hh"
-#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"
#include "mem/ruby/common/Global.hh"
#include "mem/ruby/network/Network.hh"
@@ -113,7 +113,6 @@
#include "mem/ruby/slicc_interface/NetworkMessage.hh"
#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
#include "mem/ruby/system/MemoryControl.hh"
-#include "mem/ruby/system/System.hh"
using namespace std;
diff --git a/src/mem/ruby/system/MemoryControl.hh b/src/mem/ruby/system/MemoryControl.hh
index 2b3cca603..1534851d5 100644
--- a/src/mem/ruby/system/MemoryControl.hh
+++ b/src/mem/ruby/system/MemoryControl.hh
@@ -34,14 +34,11 @@
#include <string>
#include "mem/protocol/MemoryMsg.hh"
-#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"
-#include "mem/ruby/common/Global.hh"
#include "mem/ruby/profiler/MemCntrlProfiler.hh"
#include "mem/ruby/slicc_interface/Message.hh"
#include "mem/ruby/system/AbstractMemOrCache.hh"
#include "mem/ruby/system/MemoryNode.hh"
-#include "mem/ruby/system/System.hh"
#include "params/RubyMemoryControl.hh"
#include "sim/sim_object.hh"
diff --git a/src/mem/ruby/system/PersistentTable.hh b/src/mem/ruby/system/PersistentTable.hh
index d2f58b0db..a57b3ec76 100644
--- a/src/mem/ruby/system/PersistentTable.hh
+++ b/src/mem/ruby/system/PersistentTable.hh
@@ -34,7 +34,6 @@
#include "base/hashmap.hh"
#include "mem/protocol/AccessType.hh"
#include "mem/ruby/common/Address.hh"
-#include "mem/ruby/common/Global.hh"
#include "mem/ruby/common/NetDest.hh"
#include "mem/ruby/system/MachineID.hh"
diff --git a/src/mem/ruby/system/SConscript b/src/mem/ruby/system/SConscript
index 4cf0b31ad..66d7d95bb 100644
--- a/src/mem/ruby/system/SConscript
+++ b/src/mem/ruby/system/SConscript
@@ -49,6 +49,6 @@ Source('WireBuffer.cc')
Source('MemoryNode.cc')
Source('PersistentTable.cc')
Source('RubyPort.cc')
-Source('Sequencer.cc', Werror=False)
+Source('Sequencer.cc')
Source('System.cc')
Source('TimerTable.cc')
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 9010178be..7137dcc28 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -221,10 +221,8 @@ Sequencer::printConfig(ostream& out) const
RequestStatus
Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
{
- int total_outstanding =
- m_writeRequestTable.size() + m_readRequestTable.size();
-
- assert(m_outstanding_count == total_outstanding);
+ assert(m_outstanding_count ==
+ (m_writeRequestTable.size() + m_readRequestTable.size()));
// See if we should schedule a deadlock check
if (deadlockCheckEvent.scheduled() == false) {
@@ -285,8 +283,8 @@ Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
}
g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
- total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size();
- assert(m_outstanding_count == total_outstanding);
+ assert(m_outstanding_count ==
+ (m_writeRequestTable.size() + m_readRequestTable.size()));
return RequestStatus_Ready;
}
diff --git a/src/mem/ruby/system/SparseMemory.cc b/src/mem/ruby/system/SparseMemory.cc
index fd90e2214..8e4f37c46 100644
--- a/src/mem/ruby/system/SparseMemory.cc
+++ b/src/mem/ruby/system/SparseMemory.cc
@@ -92,9 +92,7 @@ SparseMemory::recursivelyRemoveTables(SparseMapType* curTable, int curLevel)
delete nextTable;
} else {
// If at the last level, delete the directory entry
- Directory_Entry* dirEntry;
- dirEntry = (Directory_Entry*)(entryStruct->entry);
- delete dirEntry;
+ delete (AbstractEntry*)(entryStruct->entry);
}
entryStruct->entry = NULL;
}
@@ -149,7 +147,7 @@ SparseMemory::exist(const Address& address) const
// add an address to memory
void
-SparseMemory::add(const Address& address)
+SparseMemory::add(const Address& address, AbstractEntry* entry)
{
assert(address == line_address(address));
assert(!exist(address));
@@ -187,9 +185,8 @@ SparseMemory::add(const Address& address)
// if the last level, add a directory entry. Otherwise add a map.
if (level == (m_number_of_levels - 1)) {
- Directory_Entry* tempDirEntry = new Directory_Entry();
- tempDirEntry->getDataBlk().clear();
- newEntry = (void*)tempDirEntry;
+ entry->getDataBlk().clear();
+ newEntry = (void*)entry;
} else {
SparseMapType* tempMap = new SparseMapType;
newEntry = (void*)(tempMap);
@@ -262,10 +259,8 @@ SparseMemory::recursivelyRemoveLevels(const Address& address,
// if this is the last level, we have reached the Directory
// Entry and thus we should delete it including the
// SparseMemEntry container struct.
- Directory_Entry* dirEntry;
- dirEntry = (Directory_Entry*)(entryStruct->entry);
+ delete (AbstractEntry*)(entryStruct->entry);
entryStruct->entry = NULL;
- delete dirEntry;
curInfo.curTable->erase(curAddress);
m_removes_per_level[curInfo.level]++;
}
@@ -303,17 +298,14 @@ SparseMemory::remove(const Address& address)
}
// looks an address up in memory
-Directory_Entry*
+AbstractEntry*
SparseMemory::lookup(const Address& address)
{
- assert(exist(address));
assert(address == line_address(address));
- DPRINTF(RubyCache, "address: %s\n", address);
-
Address curAddress;
SparseMapType* curTable = m_map_head;
- Directory_Entry* entry = NULL;
+ AbstractEntry* entry = NULL;
// Initiallize the high bit to be the total number of bits plus
// the block offset. However the highest bit index is one less
@@ -336,13 +328,18 @@ SparseMemory::lookup(const Address& address)
// Adjust the highBit value for the next level
highBit -= m_number_of_bits_per_level[level];
- // The entry should be in the table and valid
- curTable = (SparseMapType*)(((*curTable)[curAddress]).entry);
- assert(curTable != NULL);
+ // If the address is found, move on to the next level.
+ // Otherwise, return not found
+ if (curTable->count(curAddress) != 0) {
+ curTable = (SparseMapType*)(((*curTable)[curAddress]).entry);
+ } else {
+ DPRINTF(RubyCache, "Not found\n");
+ return NULL;
+ }
}
// The last entry actually points to the Directory entry not a table
- entry = (Directory_Entry*)curTable;
+ entry = (AbstractEntry*)curTable;
return entry;
}
diff --git a/src/mem/ruby/system/SparseMemory.hh b/src/mem/ruby/system/SparseMemory.hh
index 78a3080a1..f6937ef54 100644
--- a/src/mem/ruby/system/SparseMemory.hh
+++ b/src/mem/ruby/system/SparseMemory.hh
@@ -32,7 +32,7 @@
#include <iostream>
#include "base/hashmap.hh"
-#include "mem/protocol/Directory_Entry.hh"
+#include "mem/ruby/slicc_interface/AbstractEntry.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Global.hh"
@@ -60,10 +60,10 @@ class SparseMemory
void printConfig(std::ostream& out) { }
bool exist(const Address& address) const;
- void add(const Address& address);
+ void add(const Address& address, AbstractEntry*);
void remove(const Address& address);
- Directory_Entry* lookup(const Address& address);
+ AbstractEntry* lookup(const Address& address);
// Print cache contents
void print(std::ostream& out) const;
diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh
index 15abf1c0f..704cc3b27 100644
--- a/src/mem/ruby/system/System.hh
+++ b/src/mem/ruby/system/System.hh
@@ -50,19 +50,6 @@ class Network;
class Profiler;
class Tracer;
-/*
- * This defines the number of longs (32-bits on 32 bit machines,
- * 64-bit on 64-bit AMD machines) to use to hold the set...
- * the default is 4, allowing 128 or 256 different members
- * of the set.
- *
- * This should never need to be changed for correctness reasons,
- * though increasing it will increase performance for larger
- * set sizes at the cost of a (much) larger memory footprint
- *
- */
-const int NUMBER_WORDS_PER_SET = 1;
-
class RubySystem : public SimObject
{
public:
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-29 08:43:06 +0000